公开(公告)号：US20230268913A1

公开(公告)日：2023-08-24

申请号：US18109470

申请日：2023-02-14

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： LEAF CHEN ,  JIUN-HUNG PAN

IPC分类号： H03K17/0412 ,  H03K19/0185 ,  H03K17/693

CPC分类号： H03K17/04123 ,  H03K19/018592 ,  H03K17/693

摘要： A bidirectional signal conversion circuit is configured to perform a signal conversion between a first port and a second port, and includes a switch, a first pull-up resistor, a second pull-up resistor, a first output-response enhancement circuit, and a second output-response enhancement circuit. The switch is coupled between the first port and the second port, and operates according to a bias. The first (second) pull-up resistor is coupled between the first (second) port and a high (low) voltage terminal having a high (low) voltage. The first (second) output-response enhancement circuit includes a first (second) alternative-current (AC) coupling circuit and a first (second) output-stage circuit. When the first (second) port and the second (first) port functions as an input port and an output port respectively, the first (second) output-response enhancement circuit is operable to accelerate the transient response of the output port.

公开(公告)号：US20190196568A1

公开(公告)日：2019-06-27

申请号：US16290310

申请日：2019-03-01

申请人： Intel Corporation

发明人： Vinu K. Elias ,  Sundar Ramani ,  Arvind S. Tomar ,  Jianjun Liu

IPC分类号： G06F1/3212 ,  H03K19/0185 ,  G06F1/3234

CPC分类号： G06F1/3212 ,  G06F1/3234 ,  G11C7/1057 ,  G11C7/1084 ,  G11C2207/105 ,  H03K19/018585 ,  H03K19/018592

摘要： In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

公开(公告)号：US20180126926A1

公开(公告)日：2018-05-10

申请号：US15542055

申请日：2016-01-21

申请人： BROSE FAHRZEUGTEILE GMBH & CO. KOMMANDITGESELLSCHAFT, BAMBERG

发明人： Benedikt DREMEL ,  Anto MIJAC

IPC分类号： B60R16/023 ,  B60R16/03 ,  H03K17/687 ,  H03K17/567

CPC分类号： B60R16/023 ,  B60R16/03 ,  H03K17/567 ,  H03K17/687 ,  H03K19/017509 ,  H03K19/018521 ,  H03K19/018592 ,  H03K19/0944 ,  H04B1/38 ,  H04L2012/40234

摘要： What is presented is a control device for a multi-voltage on-board electrical system of a vehicle, wherein the multi-voltage on-board electrical system has a first electrical subsystem, which is configured to be operated with a first supply voltage from a first voltage supply source, and a second electrical subsystem, which is configured to be operated with a second supply voltage from a second voltage supply source. The control device comprises: a transceiver, which is connected to ground via a first ground terminal of the first electrical subsystem and which is configured for communicating with a communication component of the first electrical subsystem; a control unit, which is connected to the same ground via a second ground terminal of the second electrical subsystem and which is configured for controlling a power component of the second electrical subsystem; a transmission path, which couples a signal output of the control unit to a signal input of the transceiver, wherein the transmission path is configured for transmitting a control signal provided by the control unit at the signal output towards the signal input of the transceiver; a diode arranged in the transmission path, the cathode terminal of said diode being coupled to the second ground terminal. Provision is furthermore made of a number of field effect transistors, wherein the number of field effect transistors on the one hand couples the transmission path to the first voltage supply source and/or to the second voltage supply source and on the other hand couples said transmission path to the first ground terminal and/or to the second ground terminal.

公开(公告)号：US20180076809A1

公开(公告)日：2018-03-15

申请号：US15813939

申请日：2017-11-15

申请人： SOCIONEXT INC.

发明人： Hajime OHMI ,  Osamu Uno ,  Masahiro Iwamoto ,  Yuichi Itonaga

IPC分类号： H03K17/081 ,  H03K19/0185 ,  H03K19/003

CPC分类号： H03K17/08104 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/018592

摘要： A semiconductor apparatus includes an internal circuit connected to a first power line to which a first power voltage is applied; a transistor including a first terminal, which is connected to a node to which an input voltage is applied, a second terminal connected to the internal circuit, and a control terminal to which a control voltage is applied; and a voltage control circuit, which is connected to the node, generating the control voltage. Further, the voltage control circuit includes a step-down circuit generating an internal voltage by lowering the input voltage applied to the node, and a switching circuit, which is connected to the first power line, generating the control voltage based on the first power voltage and the internal voltage.

公开(公告)号：US20170199555A1

公开(公告)日：2017-07-13

申请号：US15399416

申请日：2017-01-05

申请人： Siemens Aktiengesellschaft

发明人： Friedrich EPPENSTEINER ,  Majid GHAMESHLU ,  Martin MATSCHNIG ,  Herbert TAUCHER

IPC分类号： G06F1/24 ,  G06F21/70

CPC分类号： G06F1/24 ,  G06F21/70 ,  H03K17/22 ,  H03K19/01759 ,  H03K19/018592 ,  H03K19/1776

摘要： A method for adjusting a pull resistor on a contact terminal of an electronic module arranged on a printed circuit board, in particular an ASIC, after initiating a restart of the electronic module which, during a run-up process, moves the electronic module from a switched-off state into a switched-on state, wherein after initiating a restart during the run-up process from a partial circuit arranged on the electronic module and operationally ready during the run-up process, adjustment information relating to a desired adjustment of the pull resistor is retrieved from a storage unit arranged on the printed circuit board outside of the electronic module and transmitted via a contact line between the electronic module and the storage unit, where the run-up process of the electronic module is only completed after successful adjustment of the respective pull resistor based on basis the retrieved adjustment information.

公开(公告)号：US09240400B2

公开(公告)日：2016-01-19

申请号：US14043583

申请日：2013-10-01

申请人： Texas Instruments Incorporated

发明人： Venkateswara Reddy P ,  Vinayak Ghatawade ,  Rajat Chauhan

IPC分类号： H02H9/04 ,  H02H3/00 ,  H01L27/02

CPC分类号： H01L27/0248 ,  H01L27/0251 ,  H03K19/018592

摘要： An input/output (IO) circuit is provided that reduces stress on a driver without using an additional reference voltage. The IO circuit receives an overshoot voltage and an undershoot voltage in a receive mode. The IO circuit includes a driver circuit. The driver circuit includes an NMOS transistor coupled to a PMOS transistor. A pad is coupled to the driver circuit. A PMOS protect circuit is coupled to the driver circuit and the pad. An NMOS protect circuit is coupled to the driver circuit and the pad. The NMOS protect circuit is configured to be activated only for a duration of the overshoot voltage received at the pad during the receive mode and the PMOS protect circuit is configured to be activated only for a duration of the undershoot voltage received at the pad during the receive mode.

摘要翻译： 提供了一种输入/输出（IO）电路，可以减少驱动器的压力，而不需要额外的参考电压。 IO电路在接收模式下接收过冲电压和下冲电压。 IO电路包括一个驱动电路。 驱动器电路包括耦合到PMOS晶体管的NMOS晶体管。 焊盘耦合到驱动器电路。 PMOS保护电路耦合到驱动器电路和焊盘。 NMOS保护电路耦合到驱动器电路和焊盘。 NMOS保护电路被配置为仅在接收模式期间仅在焊盘处接收到的过冲电压的持续时间被激活，并且PMOS保护电路被配置为仅在接收期间在焊盘处接收到的下冲电压的持续时间被激活 模式。

公开(公告)号：US20150303924A1

公开(公告)日：2015-10-22

申请号：US14754998

申请日：2015-06-30

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Tomoaki ISOZAKI

IPC分类号： H03K19/0185 ,  H01L25/07 ,  H03K3/038

CPC分类号： H03K19/018592 ,  H01L25/07 ,  H01L27/092 ,  H01L29/78 ,  H01L2924/0002 ,  H03K3/038 ,  H03K19/018521 ,  H01L2924/00

摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area.

摘要翻译： 半导体器件包括以第一电源电压工作的第一半导体芯片和以低于第一电源电压的第二电源电压工作的第二半导体芯片，以向第一半导体芯片提供第二电源电压。 根据本发明的半导体芯片方便地用于制造半导体器件。 第一半导体芯片包括一个包括第一晶体管和第二晶体管的输出电路，其互相串联并互补地开或关。 输出电路将信号输出到第一外部输出端子。 第一半导体芯片还包括与第一和第二晶体管串联连接的第三晶体管，并且具有连接到第二输出端子的栅电极。 与在不同工作电压下工作的多个半导体芯片相互连接并将其用于半导体器件的情况相比，整个芯片面积减小，该半导体器件具有以不同于各个工作电压的电压工作的输入/输出缓冲器 导致芯片面积增加。

公开(公告)号：US09099330B2

公开(公告)日：2015-08-04

申请号：US13735661

申请日：2013-01-07

申请人： Renesas Electronics Corporation

发明人： Tomoaki Isozaki

IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/094 ,  H01L25/07 ,  H01L27/092 ,  H01L29/78 ,  H03K3/038

CPC分类号： H03K19/018592 ,  H01L25/07 ,  H01L27/092 ,  H01L29/78 ,  H01L2924/0002 ,  H03K3/038 ,  H03K19/018521 ,  H01L2924/00

摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.

摘要翻译： 半导体器件包括以第一电源电压工作的第一半导体芯片和以低于第一电源电压的第二电源电压工作的第二半导体芯片，以向第一半导体芯片提供第二电源电压。 第一半导体芯片包括一个包括第一晶体管和第二晶体管的输出电路，其互相串联并互补地开或关。 输出电路将信号输出到第一外部输出端子。 第一半导体芯片还包括与第一和第二晶体管串联连接的第三晶体管，并且具有连接到第二输出端子的栅电极。

公开(公告)号：US20150084682A1

公开(公告)日：2015-03-26

申请号：US14456931

申请日：2014-08-11

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： Chris Olson ,  Neil Calanca

IPC分类号： H03K19/0185

CPC分类号： H03K19/018592 ,  H03K19/017509 ,  H03K19/018521

摘要： Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters.

摘要翻译： 描述双路径电平移位器的方法和装置。 所描述的电平移位器装置可以包括电压 - 电流和电流 - 电压转换器。

公开(公告)号：US08913601B1

公开(公告)日：2014-12-16

申请号：US12896742

申请日：2010-10-01

申请人： Alireza S. Kaviani

发明人： Alireza S. Kaviani

IPC分类号： H04L12/28

CPC分类号： H03K19/018592 ,  G06F17/5054 ,  G06F17/5077 ,  H03K19/17736

摘要： A programmable integrated circuit is disclosed. The programmable integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of circuit blocks comprising configurable blocks; and a routing network coupled to each circuit block of the plurality of circuit blocks, the routing network enabling asynchronous data communication with the plurality of circuit blocks. Each circuit block comprises an interface portion having routing circuits coupled to the routing network, the routing circuits enabling routing data to the configurable blocks of the circuit block. A method of asynchronously routing data in a circuit block of an integrated circuit is also disclosed.

摘要翻译： 公开了一种可编程集成电路。 所述可编程集成电路包括多个电路块，所述多个电路块中的每个电路块包括可配置块; 以及耦合到所述多个电路块的每个电路块的路由网络，所述路由网络使得能够与所述多个电路块进行异步数据通信。 每个电路块包括具有耦合到路由网络的路由电路的接口部分，路由电路使能路由数据到电路块的可配置块。 还公开了在集成电路的电路块中异步路由数据的方法。