公开(公告)号：US20070015045A1

公开(公告)日：2007-01-18

申请号：US11521478

申请日：2006-09-15

Applicant: Jong-Ho Lee ,  Hae-Weon Lee ,  Joo-Sun Kim ,  Ji-Won Son ,  Hue-Sup Song ,  Hyoung-Chul Kim ,  Hwa-Young Jung

Inventor： Jong-Ho Lee ,  Hae-Weon Lee ,  Joo-Sun Kim ,  Ji-Won Son ,  Hue-Sup Song ,  Hyoung-Chul Kim ,  Hwa-Young Jung

IPC: H01M4/86

CPC classification number: H01M8/1226 ,  H01M4/0471 ,  H01M4/8605 ,  H01M4/8621 ,  H01M4/8652 ,  H01M4/8885 ,  H01M4/9016 ,  H01M4/9033 ,  H01M4/9066 ,  H01M8/1213 ,  H01M8/1246 ,  H01M8/1253 ,  H01M8/126 ,  Y02E60/525 ,  Y02P70/56

Abstract: Disclosed is an anode supporter for a solid oxide fuel cell (SOFC). The SOFC comprises an anode supporter having a high gas permeability, a high electrical conductivity, a high electrochemical activity, a high mechanical strength, and a large area; an anode functional layer for attenuating a surface defect of the anode supporter and maximizing an electrochemical activity of the anode; an electrolyte having a ultra-thin film; a cathode functional layer for removing an interface reaction between the electrolyte and the cathode and enhancing an electrochemical reaction at the cathode; a cathode having an excellent interface bonding characteristic with the cathode functional layer and a high electrical conductivity; and a current collect layer for maximizing an electrical connection between the cathode and a separator or interconnector. Accordingly, a performance of the single cell of a large area is enhanced.

Abstract translation: 公开了一种固体氧化物燃料电池（SOFC）的阳极支撑体。 SOFC包括具有高透气性，高导电性，高电化学活性，高机械强度和大面积的阳极支撑体; 阳极功能层，用于衰减阳极支撑体的表面缺陷并使阳极的电化学活性最大化; 具有超薄膜的电解质; 阴极功能层，用于去除电解质和阴极之间的界面反应并增强阴极处的电化学反应; 与阴极功能层具有优异的界面结合特性和高导电性的阴极; 以及用于最大化阴极和分离器或互连器之间的电连接的电流收集层。 因此，提高了大面积的单电池的性能。

公开(公告)号：US20060157796A1

公开(公告)日：2006-07-20

申请号：US11312806

申请日：2005-12-21

Applicant: Min-Joo Kim ,  Jong-Ho Lee ,  Sung-Kee Han ,  Hyung-Suk Jung

Inventor： Min-Joo Kim ,  Jong-Ho Lee ,  Sung-Kee Han ,  Hyung-Suk Jung

IPC: H01L29/78 ,  H01L21/4763

CPC classification number: H01L21/823835 ,  H01L21/823842

Abstract: A dual gate electrode semiconductor device and related method of formation are disclosed. The semiconductor device comprises a first gate electrode made of a metal silicide layer and a second gate electrode made of a metal layer, wherein the metal suicide is formed from the same metal as the metal layer.

Abstract translation: 公开了一种双栅电极半导体器件及相关的形成方法。 半导体器件包括由金属硅化物层制成的第一栅电极和由金属层制成的第二栅电极，其中金属硅化物由与金属层相同的金属形成。

公开(公告)号：US20060115993A1

公开(公告)日：2006-06-01

申请号：US11333741

申请日：2006-01-17

Applicant: Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

Inventor： Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

IPC: H01L21/31

CPC classification number: H01L21/02329 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

公开(公告)号：US20060054980A1

公开(公告)日：2006-03-16

申请号：US11226053

申请日：2005-09-13

Applicant: Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

Inventor： Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

IPC: H01L21/8238 ,  H01L29/94

CPC classification number: H01L21/28202 ,  H01L21/28185 ,  H01L21/28194 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/94 ,  Y10T428/265

Abstract: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M′Oy) or amorphous metal oxynitride (M′OyNz).

Abstract translation: 在一个实施例中提供了一种微电子器件的电介质多层结构，其中泄漏电流特性和介电常数得到改善。 电介质多层结构包括由非晶态硅酸盐（M 1-x Si x O x O y）或无定形硅酸盐制成的下电介质层 氮化物（M 1-x Si x O y N z N z），以及形成的上电介质层 在下部电介质层的顶部，并且由非晶金属氧化物（M'O y y）或非晶金属氧氮化物（M'O y N y） / SUB>）。

公开(公告)号：US20050145932A1

公开(公告)日：2005-07-07

申请号：US10780067

申请日：2004-02-17

Applicant: Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

Inventor： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

Abstract: A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

Abstract translation: 场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝衬底延伸超过源/漏极的绝缘层 区域交界处 晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极 侧壁朝向衬底以超出源/漏区结。 还公开了相关方法。

公开(公告)号：US20050098839A1

公开(公告)日：2005-05-12

申请号：US10930943

申请日：2004-09-01

Applicant: Jong-Ho Lee ,  Ho-Kyu Kang ,  Yun-Seok Kim ,  Seok-Joo Doh ,  Hyung-Suk Jung

Inventor： Jong-Ho Lee ,  Ho-Kyu Kang ,  Yun-Seok Kim ,  Seok-Joo Doh ,  Hyung-Suk Jung

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/94

CPC classification number: H01L21/823857

Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

Abstract translation: 半导体器件包括第一和第二晶体管器件。 第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。 第一栅极电介质位于第一衬底区域和第一栅电极之间。 第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。 第二栅极电介质位于第二基板区域和第二栅极电极之间。 第一栅极电介质包括介电常数为8以上的第一高k层。 类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。 第二高k层具有与第一高k层不同的材料组成。

公开(公告)号：US06885055B2

公开(公告)日：2005-04-26

申请号：US10358981

申请日：2003-02-04

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L21/336 ,  H01L27/108 ,  H01L29/72 ,  H01L29/786

CPC classification number: H01L29/7851 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: The present invention relates to double-gate FinFET devices and fabricating methods thereof. More particularly, the invention relates to an electrically stable double-gate FinFET device and the method of fabrication in which the Fin active region on a bulk silicon substrate where device channel and the body are to be formed has a nano-size width and is connected to the substrate and is formed with the shape of a wall along the channel length direction.The conventional double-gate MOS devices are fabricated using SOI wafers which are more expensive than bulk silicon wafers. It also has problems including the floating body effects, larger source/drain parasitic resistance, off-current increase, and deterioration in heat transfer to the substrate.

Abstract translation: 本发明涉及双栅极FinFET器件及其制造方法。 更具体地说，本发明涉及一种电稳定双栅极FinFET器件及其制造方法，其中器件沟道和器件将要形成的体硅衬底上的鳍有源区具有纳米尺寸宽度并被连接 并且沿着通道长度方向形成有壁的形状。 常规的双栅极MOS器件使用比体硅片更昂贵的SOI晶片制造。 它还具有诸如浮体效应，较大的源极/漏极寄生电阻，截止电流增加以及对衬底的热传递劣化的问题。

公开(公告)号：US06717831B2

公开(公告)日：2004-04-06

申请号：US10153391

申请日：2002-05-22

Applicant: Young-Chul Rhee ,  Young-Tak Han ,  Kwang-Ju Lee ,  Jung-Ryul Pyo ,  Jong-ho Lee

Inventor： Young-Chul Rhee ,  Young-Tak Han ,  Kwang-Ju Lee ,  Jung-Ryul Pyo ,  Jong-ho Lee

IPC: G11C1500

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) device providing higher integration density, high operation speed and low power consumption. The CAM device comprises a memory cell connected between first and second nodes, first and second data lines for transmitting first and second data signals to the first and second nodes, respectively, and first and second switching devices serially connected between a match line and a reference voltage, wherein the first switching device is controlled by the first data signal and a voltage of the first node and the second switching device is controlled by the second data signal and a voltage of the second node.

Abstract translation: 内容可寻址存储器（CAM）器件提供更高的集成密度，高操作速度和低功耗。 CAM装置包括连接在第一和第二节点之间的存储单元，分别用于将第一和第二数据信号发送到第一和第二节点的第一和第二数据线以及串联连接在匹配线和参考线之间的第一和第二开关装置 电压，其中所述第一开关器件由所述第一数据信号控制，并且所述第一节点和所述第二开关器件的电压由所述第二数据信号和所述第二节点的电压控制。

公开(公告)号：US06303441B1

公开(公告)日：2001-10-16

申请号：US09306915

申请日：1999-05-07

Applicant: Young June Park ,  Jong Ho Lee ,  Hyeok Jae Lee

Inventor： Young June Park ,  Jong Ho Lee ,  Hyeok Jae Lee

IPC: H01L21336

CPC classification number: H01L29/66613 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

Abstract: A semiconductor device and a method for fabricating the same is disclosed, which minimizes device degradation, minimizes noises, and simplifies the fabrication process. The device includes a substrate having a first semiconductor layer, a buried insulating film, and a second semiconductor layer stacked; a field oxide film for separating the second semiconductor layer into a first region and a second region; a recess region formed in a particular region of the second region; gate insulating films and gate electrodes formed in stacks on each of a particular region in the first region and the recess region in the second region; first impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the first region; and second impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the recess region in the second region so that the second semiconductor layer below the gate electrode is fully depleted.

Abstract translation: 公开了一种半导体器件及其制造方法，其使器件劣化最小化，使噪声最小化并简化制造工艺。 该器件包括具有第一半导体层，埋入绝缘膜和堆叠的第二半导体层的衬底; 用于将第二半导体层分离成第一区域和第二区域的场氧化物膜; 形成在所述第二区域的特定区域中的凹部区域; 在第一区域中的特定区域和第二区域中的凹陷区域中的每一个上堆叠形成栅极绝缘膜和栅电极; 在所述第一区域中的所述栅电极的两侧上形成在所述第二半导体层的表面中的第一杂质区; 以及在所述第二区域中的所述凹部区域中的所述栅电极的两侧上形成在所述第二半导体层的表面中的第二杂质区域，使得所述栅电极下方的所述第二半导体层完全耗尽。

公开(公告)号：US6165842A

公开(公告)日：2000-12-26

申请号：US353321

申请日：1999-07-14

Applicant: Hyung Cheol Shin ,  Ii Gweon Kim ,  Jong Ho Lee

Inventor： Hyung Cheol Shin ,  Ii Gweon Kim ,  Jong Ho Lee

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: B82Y10/00 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  Y10S438/962

Abstract: The present invention proposes a method for fabricating a non-volatile memory device using nano-crystals with an increased etching rate and an increased oxidation rate at the grain boundary, which is used in high-speed and low power consumption device. The method for fabricating a non-volatile memory device using nano-crystal dots comprises following processes. First process is to fabricate a tunneling dielectric 204 and a thin amorphous silicon continuous film. Second process is to fabricate a poly-silicon layer by poly-crystallizing the amorphous silicon film. Third process is to fabricate nano-crystals 212 by etching the poly-silicon layer. Fourth process is to fabricate an interlayer dielectric 214 on the nano-crystals 212. Fifth process is to attach a poly-silicon film to the interlayer dielectric 214 and fabricate a gate 216 and interconnects 220.

Abstract translation: 本发明提出了一种使用纳米晶体制造非晶体存储器件的方法，所述非易失性存储器件具有在高速和低功耗器件中使用的具有增加的蚀刻速率和增加的晶界氧化速率的纳米晶体。 使用纳米晶体点制造非易失性存储器件的方法包括以下处理。 第一种方法是制造隧道电介质204和薄的非晶硅连续膜。 第二工艺是通过使非晶硅膜多结晶来制造多晶硅层。 第三工艺是通过蚀刻多晶硅层来制造纳米晶体212。 第四种方法是在纳米晶体212上制造层间电介质214.第五种方法是将多晶硅膜附着到层间电介质214上并制造栅极216和互连220。