公开(公告)号：US06288710B1

公开(公告)日：2001-09-11

申请号：US09372937

申请日：1999-08-12

Applicant: Wen-Chin Lee ,  Shun-Pin Lin

Inventor： Wen-Chin Lee ,  Shun-Pin Lin

IPC: G09G500

CPC classification number: G06F3/046

Abstract: In a method and apparatus for detecting the position of a coordinate probe relative to a digitizing tablet, a sensing coil grid provided on a working region of the tablet includes a plurality of sensing coils, each of which is U-shaped and has a front section and a grounded rear section. The coils are arranged in parallel along an axis of the working region in an overlapping manner with the front sections of consecutive ones of the coils being arranged in succession, and with the rear sections of the coils also being arranged in succession. During the sequential scanning of the coils in order to detect the electric currents induced therein and to generate a grid signal when the coordinate probe is disposed on the working region, a phase selection circuit inverts one of front and rear half-cycles of the grid signal, depending on whether a front scanning or rear scanning operation is being performed, and a signal processing circuit detects the presence of a predetermined transition of the inverted signal from the phase selection circuit. The signal processing circuit generates a count output corresponding to time elapsed before the predetermined transition is detected, and the count output is converted by a processor into a coordinate of the coordinate probe along the axis of the working region of the tablet.

Abstract translation: 在用于检测坐标探针相对于数字化图形输入板的位置的方法和装置中，设置在图形输入板的工作区域上的感测线圈格栅包括多个感测线圈，每个感测线圈为U形，并且具有前部 和接地后部。 线圈沿着工作区域的轴线以重叠的方式平行布置，连续的线圈的前部部分被连续布置，并且线圈的后部段也被连续布置。 在线圈的顺序扫描期间，为了检测其中感应到的电流并且当坐标探针设置在工作区域上时产生电网信号，相位选择电路将电网信号的前半周期和后半周期中的一个反相 取决于正在执行正面扫描还是后扫描操作，并且信号处理电路检测来自相位选择电路的反相信号的预定转换的存在。 信号处理电路产生对应于在检测到预定转换之前经过的时间的计数输出，并且计数输出由处理器转换成沿着平板电脑的工作区域的轴的坐标探针的坐标。

公开(公告)号：US08569837B2

公开(公告)日：2013-10-29

申请号：US11800615

申请日：2007-05-07

Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅电极相邻的深源/漏区; 深源/漏区上的硅化物区; 以及在硅化物区域和栅电极之间的升高的金属化源极/漏极区域。 升高的金属化源极/漏极区域邻接硅化物区域。

公开(公告)号：US08546176B2

公开(公告)日：2013-10-01

申请号：US12765407

申请日：2010-04-22

Applicant: Wen-Chin Lee ,  Wen-Tsai Yen ,  Ding-Yuan Chen ,  Liang-Sheng Yu ,  Yu-Han Chang

Inventor： Wen-Chin Lee ,  Wen-Tsai Yen ,  Ding-Yuan Chen ,  Liang-Sheng Yu ,  Yu-Han Chang

IPC: H01L21/00

CPC classification number: C23C14/3464 ,  C23C14/0623 ,  H01L31/0322 ,  Y02E10/541 ,  Y02P70/521

Abstract: Sulfur-containing chalcogenide absorbers in thin film solar cell are manufactured by sequential sputtering or co-sputtering targets, one of which contains a sulfur compound, onto a substrate and then annealing the substrate. The anneal is performed in a non-sulfur containing environment and avoids the use of hazardous hydrogen sulfide gas. A sulfurized chalcogenide is formed having a sulfur concentration gradient.

Abstract translation: 在薄膜太阳能电池中的含硫硫属元素化物吸收剂通过在衬底上顺序溅射或共溅射靶（其中一个含有硫化合物）然后对衬底进行退火来制造。 退火在不含硫的环境中进行，避免使用危险的硫化氢气体。 形成具有硫浓度梯度的硫化硫族化物。

公开(公告)号：US20130167916A1

公开(公告)日：2013-07-04

申请号：US13338292

申请日：2011-12-28

Applicant: Wen-Chin LEE ,  Liang-Sheng YU

Inventor： Wen-Chin LEE ,  Liang-Sheng YU

IPC: H01L31/0352 ,  H01L31/18

CPC classification number: H01L31/0749 ,  H01L31/02363 ,  H01L31/0322 ,  H01L31/035281 ,  H01L31/03923 ,  H01L31/046 ,  H01L31/0465 ,  Y02E10/541

Abstract: A thin film photovoltaic cell and method for forming the same. The thin film photovoltaic cell includes a first electrode layer formed on a substrate. An absorber layer of a first dopant-type is formed on the first electrode layer. The absorber layer has an opening extending partially into the absorber layer from a top surface of the absorber layer. The opening has side walls and a bottom surface. A buffer layer of a second dopant type is formed on the top surface of the absorber layer, the side walls of the opening and the bottom surface of the opening A second electrode layer is formed on the buffer layer.

Abstract translation: 一种薄膜光伏电池及其形成方法。 薄膜光伏电池包括形成在基板上的第一电极层。 第一掺杂剂型的吸收层形成在第一电极层上。 吸收层具有从吸收体层的上表面部分地延伸到吸收体层中的开口。 开口具有侧壁和底面。 在吸收体层的顶面形成有第二掺杂剂型的缓冲层，在缓冲层上形成开口侧壁和开口底面第二电极层。

公开(公告)号：US08466505B2

公开(公告)日：2013-06-18

申请号：US11077479

申请日：2005-03-10

Applicant: Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

Inventor： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/8616

Abstract: A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.

Abstract translation: 一种半导体器件及其制造方法。 半导体器件包括栅极结构，其包括在衬底上的隧道氧化物; 隧道氧化物上的浮动栅; 在浮动栅极上的电介质; 以及电介质上的控制栅极。 半导体器件还包括：沿着栅极结构的相对边缘的间隔物; 掺杂有与栅极结构的第一边缘横向间隔开的第一类型掺杂物的第一杂质区; 以及掺杂有与第一类型相反的第二类型掺杂剂的第二杂质区，漏极基本上在漏极间隔下方并且基本上与栅极结构的第二边缘对准。

公开(公告)号：US08426298B2

公开(公告)日：2013-04-23

申请号：US13113530

申请日：2011-05-23

Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

Abstract translation: 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源/漏延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

公开(公告)号：US20120237721A1

公开(公告)日：2012-09-20

申请号：US13461006

申请日：2012-05-01

Applicant: CHENG-HSIEN LIN ,  YAO-WEN BAI ,  WEN-CHIN LEE ,  RUI ZHANG ,  KAI-LI JIANG ,  CHEN FENG

Inventor： CHENG-HSIEN LIN ,  YAO-WEN BAI ,  WEN-CHIN LEE ,  RUI ZHANG ,  KAI-LI JIANG ,  CHEN FENG

IPC: B32B5/12 ,  B82Y30/00

CPC classification number: H05K9/009 ,  B29C70/882 ,  B29C70/885 ,  B29K2105/167 ,  C08L2666/76 ,  H05K9/0083 ,  H05K9/0088 ,  Y10S977/784 ,  Y10S977/789 ,  Y10T428/24132 ,  Y10T428/249979

Abstract: An electromagnetic shielding composite includes a polymer and a carbon nanotube film structure. The carbon nanotube structure includes a number of carbon nanotubes disposed in the polymer. The number of carbon nanotubes are parallel with each other.

Abstract translation: 电磁屏蔽复合材料包括聚合物和碳纳米管薄膜结构。 碳纳米管结构包括设置在聚合物中的多个碳纳米管。 碳纳米管的数量彼此平行。

公开(公告)号：US08084305B2

公开(公告)日：2011-12-27

申请号：US12036616

申请日：2008-02-25

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

Abstract translation: 半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。

公开(公告)号：US08039284B2

公开(公告)日：2011-10-18

申请号：US11640713

申请日：2006-12-18

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC: H01L21/00 ,  H01L29/84

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming a PMOS device at the surface of the semiconductor substrate comprising forming a second source/drain electrode on a second source/drain region of the PMOS device, wherein the second source/drain electrode has a second barrier height, and wherein the first barrier height is different from the second barrier height; forming a first stressed film having a first intrinsic stress over the NMOS device; and forming a second stressed film having a second intrinsic stress over the PMOS device, wherein the first intrinsic stress is more tensile than the second intrinsic stress.

Abstract translation: 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底的表面上形成NMOS器件，其包括在所述NMOS器件的第一源极/漏极区域上形成第一源极/漏极，其中所述第一源极/漏极具有第一势垒高度; 在所述半导体衬底的表面上形成PMOS器件，包括在所述PMOS器件的第二源极/漏极区域上形成第二源极/漏极，其中所述第二源极/漏极具有第二势垒高度，并且其中所述第一势垒高度 与第二屏障高度不同; 在NMOS器件上形成具有第一固有应力的第一应力膜; 以及在所述PMOS器件上形成具有第二固有应力的第二应力膜，其中所述第一本征应力比所述第二固有应力更具拉伸力。

公开(公告)号：US20110117724A1

公开(公告)日：2011-05-19

申请号：US13013296

申请日：2011-01-25

Applicant: Chih-Hsin KO ,  Yee-Chia YEO ,  Wen-Chin LEE ,  Chung-Hu GE

Inventor： Chih-Hsin KO ,  Yee-Chia YEO ,  Wen-Chin LEE ,  Chung-Hu GE

IPC: H01L21/762 ,  H01L21/763

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

Abstract translation: 公开了一种用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。