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    Methods for forming high-performing dual-damascene interconnect structures
    121.
    发明授权
    Methods for forming high-performing dual-damascene interconnect structures 有权
    用于形成高性能双镶嵌互连结构的方法

    公开(公告)号：US6071809A

    公开(公告)日：2000-06-06

    申请号：US161176

    申请日：1998-09-25

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

    CPC classification number: H01L21/7681 ,  H01L21/76819 ,  H01L21/7684 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002

    Abstract: Dual damascene methods and structures are provided for IC interconnects which use a dual-damascene process incorporating a low-k dielectric material, high conductivity metal, and an improved hard mask scheme. A pair of hard masks are employed: a silicon dioxide layer and a silicon nitride layer, wherein the silicon dioxide layer acts to protect the silicon nitride layer during dual damascene etch processing, but is subsequently sacrificed during CMP, allowing the silicon nitride layer to act as a the CMP hard mask. In this way, delamination of the low-k material is prevented, and any copper-contaminated silicon dioxide material is removed.

    Abstract translation: 提供了双重镶嵌方法和结构用于IC互连，其使用结合低k电介质材料，高导电性金属和改进的硬掩模方案的双镶嵌工艺。 使用一对硬掩模：二氧化硅层和氮化硅层，其中二氧化硅层用于在双镶嵌蚀刻处理期间保护氮化硅层，但随后在CMP期间被牺牲，允许氮化硅层起作用 作为CMP硬掩模。 以这种方式，可以防止低k材料的分层，并且去除任何铜污染的二氧化硅材料。

    STABILIZED WHOLE GRAIN FLOUR AND METHOD OF MAKING
    124.
    发明申请
    STABILIZED WHOLE GRAIN FLOUR AND METHOD OF MAKING 审中-公开
    稳定的全谷物和制备方法

    公开(公告)号：US20140106052A1

    公开(公告)日：2014-04-17

    申请号：US13985712

    申请日：2012-02-24

    Applicant: Derwin G. Hawley ,  Edward D. Howey ,  William H. Cleaver ,  Lynn C. Haynes ,  Desiree S. Bramble ,  Ning Zhou ,  Bin Zhao ,  Timothy S. Hansen ,  Domenico R. Cassone ,  Sarwat Gabriel

    Inventor： Derwin G. Hawley ,  Edward D. Howey ,  William H. Cleaver ,  Lynn C. Haynes ,  Desiree S. Bramble ,  Ning Zhou ,  Bin Zhao ,  Timothy S. Hansen ,  Domenico R. Cassone ,  Sarwat Gabriel

    IPC: A21D6/00

    CPC classification number: A21D6/003 ,  A21D13/02 ,  A23L7/115 ,  A23L7/197 ,  B02C9/04 ,  B02C23/08

    Abstract: Stabilized whole grain flours having a fine particle size and which exhibit good baking functionality are produced with high throughput using two bran and germ fractions and an endosperm fraction. One bran and germ fraction is a coarse fraction which is subjected to two stage grinding, but the second bran and germ fraction is a low ash, fine bran and germ fraction which is sufficiently fine so that it does not need to be subjected to grinding thereby reducing starch damage and increasing production with reduced grinding equipment load. Portions of the coarse bran and germ fraction which are ground in the first grinding stage to a sufficient fineness are separated out and not subjected to additional grinding further reducing starch damage and increasing production. The bran and germ fractions may be combined, subjected to stabilization, and combined with the endosperm fraction to obtain a stabilized whole grain flour.

    Abstract translation: 使用两个麸皮和胚芽部分和胚乳部分以高产量生产具有细粒度并且表现出良好烘烤功能的稳定的全谷物面粉。 一个麸皮和胚芽部分是经过两阶段研磨的粗级分，但是第二糠和胚芽级分是足够细的低灰分，细糠和胚芽分数，从而不需要进行研磨 降低粉碎设备负荷，减少淀粉损伤并增加生产。 将在第一研磨阶段研磨的粗糠和胚芽级分的部分分离成足够的细度，并且不进行另外的研磨，进一步减少淀粉损伤并增加产量。 可以将麸皮和胚芽部分组合，进行稳定化，并与胚乳部分组合以获得稳定的全谷物粉末。

    VLPs derived from cells that do not express a viral matrix or core protein
    125.
    发明授权
    VLPs derived from cells that do not express a viral matrix or core protein 有权
    源自不表达病毒基质或核心蛋白的细胞的VLP

    公开(公告)号：US08697088B2

    公开(公告)日：2014-04-15

    申请号：US12127625

    申请日：2008-05-27

    Applicant: Gale Smith ,  Peter Pushko ,  Kutub Mahmood ,  Bin Zhao

    Inventor： Gale Smith ,  Peter Pushko ,  Kutub Mahmood ,  Bin Zhao

    IPC: A61K39/145 ,  C12N15/44

    CPC classification number: A61K39/145 ,  A61K2039/5258 ,  C07K2319/00 ,  C12N7/00 ,  C12N2710/16723 ,  C12N2760/16123

    Abstract: The present invention discloses novel influenza virus-like particles (VLPs) that contain chimeric proteins or influenza membrane proteins. The chimeric proteins are derived from fragments of influenza membrane proteins fused to heterologous proteins. The invention includes antigenic formulations and vaccines comprising VLPs of the invention as well as methods of making and administering VLPs to vertebrates, including methods of inducing immunity to infections, such as influenza.

    Abstract translation: 本发明公开了含有嵌合蛋白或流感病毒膜蛋白的新型流感病毒样颗粒（VLPs）。 嵌合蛋白质衍生自与异源蛋白质融合的流感病毒膜蛋白片段。 本发明包括抗原制剂和包含本发明的VLP的疫苗以及向脊椎动物制备和施用VLP的方法，包括诱导感染免疫的方法，例如流感。

    Serial cascade of minimium tail voltages of subsets of LED strings for dynamic power control in LED displays
    128.
    发明授权
    Serial cascade of minimium tail voltages of subsets of LED strings for dynamic power control in LED displays 有权
    用于LED显示屏中动态功率控制的LED灯串子串的最小尾电压串联级联

    公开(公告)号：US08493003B2

    公开(公告)日：2013-07-23

    申请号：US12690972

    申请日：2010-01-21

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: H05B37/02

    CPC classification number: H05B33/0818 ,  H05B33/0857

    Abstract: A light emitting diode (LED) system implements a power management technique. The LED system includes a plurality of LED drivers connected in series, each LED driver configured to regulate the current flowing through a corresponding subset of a plurality of LED strings. Each LED driver determines the tail voltages of the one or more LED strings of the corresponding subset. Each LED driver, except for the first LED driver in the series, also receives a voltage representative of the minimum tail voltage of the other subsets regulated by the upstream LED drivers. Each LED driver then provides the lowest of the voltage received from the upstream LED driver and the one or more tail voltages of the corresponding subset to the downstream LED driver. In this manner a voltage representative of the minimum tail voltage of the plurality of LED strings is cascaded through the series. A feedback controller monitors the minimum tail voltage represented by this cascaded voltage and accordingly adjusts an output voltage provided to the head ends of the plurality of LED strings.

    Abstract translation: 发光二极管（LED）系统实现电源管理技术。 LED系统包括串联连接的多个LED驱动器，每个LED驱动器配置成调节流过多个LED串的相应子集的电流。 每个LED驱动器确定相应子集的一个或多个LED串的尾部电压。 除了该系列中的第一个LED驱动器之外，每个LED驱动器还接收代表由上游LED驱动器调节的其他子集的最小尾电压的电压。 然后，每个LED驱动器将从上游LED驱动器接收的最低电压和相应子集的一个或多个尾部电压提供给下游LED驱动器。 以这种方式，表示多个LED串的最小尾电压的电压通过该系列级联。 反馈控制器监视由该级联电压表示的最小尾电压，并相应地调节提供给多个LED串的头端的输出电压。

    Magnetic recording head, head gimbal assembly, and disk drive unit with the same
    130.
    发明授权
    Magnetic recording head, head gimbal assembly, and disk drive unit with the same 有权
    磁记录头，磁头万向节组件和磁盘驱动单元相同

    公开(公告)号：US08320081B2

    公开(公告)日：2012-11-27

    申请号：US12662503

    申请日：2010-04-20

    Applicant: Shenkuang Chou ,  Liping Peng ,  Kayip Wong ,  Yanbin Wang ,  Lu Xiao ,  Bin Zhao

    Inventor： Shenkuang Chou ,  Liping Peng ,  Kayip Wong ,  Yanbin Wang ,  Lu Xiao ,  Bin Zhao

    IPC: G11B5/60

    CPC classification number: G11B5/4853 ,  Y10T428/1171 ,  Y10T428/1193

    Abstract: A magnetic recording head includes a trailing surface and a plurality of bonding pads arranged on the trailing surface and in a row adapted for both bonding and testing. Each of the bonding pads has at least one side portion being coated with electrically conductive solder nonwettable coat to prevent short circuit between the adjacent bonding pads. The invention also discloses a head gimbal assembly with the magnetic recording head and a disk drive unit having such head gimbal assembly.

    Abstract translation: 磁记录头包括后表面和布置在后表面上并且适于粘合和测试的行中的多个接合焊盘。 每个接合焊盘具有涂覆有导电焊料不可润湿涂层的至少一个侧部，以防止相邻接合焊盘之间的短路。 本发明还公开了一种具有磁记录头的磁头万向架组件和具有这种磁头万向架组件的磁盘驱动单元。

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