公开(公告)号：US07522847B2

公开(公告)日：2009-04-21

申请号：US10774724

申请日：2004-02-09

Applicant: Afshin Momtaz ,  Mario Caresosa

Inventor： Afshin Momtaz ,  Mario Caresosa

IPC: H04B10/00

CPC classification number: H04B10/66 ,  H04L25/03038 ,  H04L25/03057 ,  H04L2025/0349

Abstract: A communication system having a transmitter transmits an information signal over a communication media and a receiver coupled to the communication media receives the transmitted information signal. The receiver includes a continuous time filter having an adjustable bandwidth for linearly equalizing the transmitted information signal as a function of the adjustable bandwidth. A decision feedback equalizer coupled to the continuous time filter then reduces inter-symbol interference in the filtered information signal.

Abstract translation: 具有发射机的通信系统通过通信介质发送信息信号，并且耦合到通信媒体的接收机接收所发送的信息信号。 接收机包括具有可调节带宽的连续时间滤波器，用于作为可调节带宽的函数线性地均衡所发送的信息信号。 耦合到连续时间滤波器的判决反馈均衡器然后减少滤波信息信号中的符号间干扰。

公开(公告)号：US07501873B2

公开(公告)日：2009-03-10

申请号：US11731713

申请日：2007-03-30

Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

IPC: H03L5/00

CPC classification number: H03K5/151 ,  H03K5/003 ,  H03K5/086

Abstract: Embodiments of threshold adjustment circuits are disclosed. An example circuit includes a first differential pair of first and second thin oxide transistors. The first and second thin oxide transistors decrease a DC voltage component of a first and/or second component of an input signal of the circuit. The example circuit further includes a second differential pair of third and fourth thin oxide transistors. The second and third thin oxide transistors increase a DC voltage component of the first and/or the second component of the input signal. The example circuit also includes a power supply that provides a supply voltage to the circuit, the power supply having a voltage level above a reliability level of the thin oxide transistors. In the example circuit, each of the differential pair thin oxide transistors is switched by a signal that keeps each of the first, second, third, and fourth thin oxide transistors operating in saturation.

Abstract translation: 公开了阈值调整电路的实施例。 示例电路包括第一和第二薄氧化物晶体管的第一差分对。 第一和第二薄氧化物晶体管降低电路的输入信号的第一和/或第二分量的DC电压分量。 示例电路还包括第三和第四薄氧化物晶体管的第二差分对。 第二和第三薄氧化物晶体管增加输入信号的第一和/或第二分量的直流电压分量。 示例电路还包括向电路提供电源电压的电源，电源具有高于薄氧化物晶体管的可靠性水平的电压电平。 在示例电路中，通过使第一，第二，第三和第四薄氧化物晶体管中的每一个饱和的信号切换差分对薄氧化物晶体管中的每一个。

公开(公告)号：US20080297251A1

公开(公告)日：2008-12-04

申请号：US12190107

申请日：2008-08-12

Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45197 ,  H03F2203/45366 ,  H03F2203/45492 ,  H03F2203/45494 ,  H03F2203/45506 ,  H03F2203/45652 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03G1/0088 ,  H03G3/001

Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.

公开(公告)号：US20080192816A1

公开(公告)日：2008-08-14

申请号：US11730079

申请日：2007-03-29

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03H7/30

CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

Abstract: An equalizer is disclosed that compensates for non-linear effects resulting from a transmitter, a receiver, and/or a communication channel in a communication system. A non-linear decision feedback equalizer compensates for the non-linear effects impressed onto a received symbol by selecting between equalization coefficients based upon a previous received symbol. The received symbol may be represented in form of logic signals based on the binary number system. The two symbols most commonly chosen to represent the two logic values taken on by binary symbols are binary zero and binary one. When the previous received symbol is a binary zero, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary zero to compensate for the non-linear effects impressed onto the received symbol. Likewise, when the previous received symbol is a binary one, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary one to compensate for the non-linear effects impressed onto the received symbol.

Abstract translation: 公开了一种补偿由通信系统中的发射机，接收机和/或通信信道产生的非线性效应的均衡器。 非线性判决反馈均衡器通过基于先前接收到的符号在均衡系数之间进行选择来补偿对接收到的符号施加的非线性效应。 所接收的符号可以以基于二进制数系统的逻辑信号的形式表示。 最常选择用于表示由二进制符号取代的两个逻辑值的两个符号是二进制零和二进制。 当前一个接收到的符号是二进制零时，非线性判决反馈均衡器选择对应于二进制零的均衡系数来补偿被加载到接收符号上的非线性效应。 同样地，当前一个接收到的符号是二进制符号时，非线性判决反馈均衡器选择对应于二进制符号的均衡系数来补偿被加载到接收符号上的非线性效应。

公开(公告)号：US20080048897A1

公开(公告)日：2008-02-28

申请号：US11845765

申请日：2007-08-27

Applicant: Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

Inventor： Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

IPC: H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0836 ,  H03M1/1215 ,  H03M1/183

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract translation: 实施例包括一种用于对通过通信信道接收的电磁信号进行色散补偿的系统，该电磁信号以符号速率承载信息。 可以使用交错模数转换器（“ADC”）块，其中交织的ADC块可以被配置为从电磁信号生成多个数字采样的信号。 交织的均衡器块可以被配置为数字地处理由ADC块产生的数字采样信号中的每一个以产生多个数字均衡的信号。 多路复用器可以被配置为将数字均衡的信号聚合成复合输出信号。

公开(公告)号：US20080048896A1

公开(公告)日：2008-02-28

申请号：US11845762

申请日：2007-08-27

Applicant: Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

Inventor： Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

IPC: H03M1/12

CPC classification number: H03M1/0836 ,  H03M1/1215 ,  H03M1/183

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract translation: 实施例包括一种用于对通过通信信道接收的电磁信号进行色散补偿的系统，该电磁信号以符号速率承载信息。 可以使用交错模数转换器（“ADC”）块，其中交织的ADC块可以被配置为从电磁信号生成多个数字采样的信号。 交织的均衡器块可以被配置为数字地处理由ADC块产生的数字采样信号中的每一个以产生多个数字均衡的信号。 多路复用器可以被配置为将数字均衡的信号聚合成复合输出信号。

公开(公告)号：US07325175B2

公开(公告)日：2008-01-29

申请号：US11123355

申请日：2005-05-04

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: G06F11/00

CPC classification number: H03L7/0814 ,  H03L7/087 ,  H03L7/10 ,  H03M1/1245 ,  H04L7/0058 ,  H04L7/033 ,  H04L25/03146

Abstract: A system may adjust the times at which data is sampled by separate sampling mechanisms. Here, it may be desirable to ensure that one sampler samples data at substantially the same time as the other sampler. For example, output data from a high speed sampler that samples received data may be compared with an output of an analog to digital converter that samples the received data at a lower data rate. This difference or relative error may be accumulated over a period of time for given values of delay applied to the clock for the analog to digital converter. In this way, a delay value that minimizes the relative error may be selected as a desired delay value.

Abstract translation: 系统可以通过单独的采样机制来调整采样数据的时间。 在这里，可能需要确保一个采样器在与其他采样器基本相同的时间采样数据。 例如，可以将来自接收数据采样的高速采样器的输出数据与以较低数据速率对接收到的数据进行采样的模数转换器的输出进行比较。 对于给予模数转换器的时钟的延迟的给定值，该差异或相对误差可以在一段时间内累积。 以这种方式，可以将相对误差最小化的延迟值选择为期望的延迟值。

公开(公告)号：US20070110148A1

公开(公告)日：2007-05-17

申请号：US11281204

申请日：2005-11-15

Applicant: Afshin Momtaz ,  Rajesh Satapathy ,  Chung-Jue Chen

Inventor： Afshin Momtaz ,  Rajesh Satapathy ,  Chung-Jue Chen

IPC: H03K5/159 ,  H04L27/08 ,  H04B1/10

CPC classification number: H04L25/03057 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L2025/0349 ,  H04L2025/03617 ,  H04L2025/03662 ,  H04L2025/03687 ,  H04L2025/037

Abstract: A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops.

Abstract translation: 搜索引擎选择接收均衡器的初始系数。 搜索引擎可以并入到包括判决反馈均衡器和时钟和数据恢复电路的通信接收器中。 这里，搜索引擎可以初始化可以控制例如判决反馈均衡器，时钟和数据恢复电路以及连续时间滤波器的操作的各种适配环路。 接收机可以包括用于产生一些适配环路的软判决数据的模拟 - 数字转换器。

公开(公告)号：US07170964B2

公开(公告)日：2007-01-30

申请号：US10355848

申请日：2003-01-31

Applicant: Namik Kocaman ,  Afshin Momtaz

Inventor： Namik Kocaman ,  Afshin Momtaz

IPC: H03D3/24

CPC classification number: H04L7/0331 ,  H03L7/091 ,  H03L7/093

Abstract: A timing recovery circuit comprises a data-driven phase detector and a digital loop filter. The data-driven phase detector is operably coupled to determine at least a phase difference between an input signal and a feedback clock signal to produce a difference signal. Determining the phase difference can comprise digitally determining a timing difference between the input signal and the feedback clock signal, digitally determining a transition of the input signal to produce a transition detect signal, and digitally updating the timing difference based on the transition detect signal and the feedback clock signal. The timing difference can be digitally updated by pre-filtering the timing difference BY TAKING EVERY N TRANSITON OR AVERAGE OF EVERY N TRANSITIONS at a digital pre-filter, based on a pre-filter clock signal produced from the transition detect signal and the feedback clock signal, to produce the difference signal. The loop filter is operably coupled to filter the difference signal to produce a control voltage.

Abstract translation: 定时恢复电路包括数据驱动相位检测器和数字环路滤波器。 数据驱动相位检测器可操作地耦合以确定输入信号和反馈时钟信号之间的至少一个相位差，以产生差分信号。 确定相位差可以包括数字地确定输入信号和反馈时钟信号之间的定时差，数字地确定输入信号的转变以产生转换检测信号，并且基于转换检测信号和数字地更新定时差 反馈时钟信号。 基于从转换检测信号和反馈时钟产生的预滤波器时钟信号，通过对数字预滤波器进行每次N个转换的每次N次转换或每次N个转换的平均值来预定时器差异，可以对定时差异进行数字更新 信号，产生差分信号。 环路滤波器可操作地耦合以滤除差分信号以产生控制电压。

公开(公告)号：US20060261895A1

公开(公告)日：2006-11-23

申请号：US11135208

申请日：2005-05-23

Applicant: Namik Kocaman ,  Afshin Momtaz

Inventor： Namik Kocaman ,  Afshin Momtaz

IPC: H03G3/10

CPC classification number: H03G3/3052 ,  H03G3/001 ,  H03G3/3036

Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes multiple comparators to provide constant bandwidth tracking and step response, as well as fine granularity for decision directed convergence. In one embodiment, an odd number of comparators is used with square-law scaling at the output to achieve constant bandwidth step response for a wide range of input amplitude changes.

Abstract translation: 一种用于自动增益控制（AGC）回路的方法和装置，其利用多个比较器来提供恒定的带宽跟踪和阶跃响应，以及用于决策定向收敛的细粒度。 在一个实施例中，使用奇数比较器，在输出处使用平方律缩放来实现宽范围的输入幅度变化的恒定带宽阶跃响应。