公开(公告)号：US10128356B2

公开(公告)日：2018-11-13

申请号：US15118843

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Roza Kotlyar ,  Ian A. Young

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/18 ,  H01L29/78 ,  H01L29/88 ,  H01L29/739 ,  G06F3/041 ,  H01L23/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/165 ,  H01L29/205

Abstract: Tunneling field effect transistors (TFETs) are described herein. In an example, a TFET includes a pocket disposed near a junction of a source region, wherein the pocket region is formed from a material having lower percentage of one type of atom than percentage of the one type of atom in source, channel, and drain regions.

公开(公告)号：US20170207222A1

公开(公告)日：2017-07-20

申请号：US15474689

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20170133493A1

公开(公告)日：2017-05-11

申请号：US15410548

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, JR. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

公开(公告)号：US20170018304A1

公开(公告)日：2017-01-19

申请号：US15282484

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Rafael Rios ,  Ian A. Young

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C11/412 ,  H01L27/1104 ,  H03K3/356104

Abstract: Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.

Abstract translation: 实施例包括用于移位电压电平的电路的装置，方法和系统。 电路可以包括第一反相器，其包括耦合以传递低电压信号的第一晶体管和耦合以接收低电压信号的第二反相器。 电路还可以包括第二晶体管，其被耦合以从第二反相器接收低电压信号，以用作反馈装置并产生高电压信号。 在实施例中，第一晶体管不对称地导通，以防止高电压信号到低电压域的交叉。 还描述了低电压存储器阵列。 在实施例中，用于移位电压电平的电路可以有助于包括低电压域的低电压存储器阵列的逻辑部件与高电压域的逻辑部件之间的通信。 还可以描述另外的实施例。

公开(公告)号：US20160276440A1

公开(公告)日：2016-09-22

申请号：US15037296

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Roza KOTLYAR ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ian A. YOUNG

IPC: H01L29/12 ,  H01L29/205 ,  H01L29/165 ,  G11C5/06 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/125 ,  G11C5/06 ,  H01L29/0669 ,  H01L29/165 ,  H01L29/205 ,  H01L29/7391 ,  H01L29/7831

Abstract: Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.

Abstract translation: 本文所述的本发明的实施例包括具有漏极区域，具有与漏极区域相反的导电类型的源极区域的沟道场效应晶体管（TFET），设置在源极区域和漏极区域之间的沟道区域，栅极设置在 沟道区域和设置在源区域和沟道区域的结点附近的异质袋。 异质袋包括不同于沟道区的半导体材料，并且包括小于沟道区中的带隙的隧穿势垒，并且在施加到栅极的电压时在通道区中形成量子阱以增加通过TFET晶体管的电流 门高于阈值电压。