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    Technologies for efficient LZ77-based data decompression
    121.
    发明授权
    Technologies for efficient LZ77-based data decompression 有权
    技术用于高效的基于LZ77的数据解压缩

    公开(公告)号：US09524169B2

    公开(公告)日：2016-12-20

    申请号：US14494766

    申请日：2014-09-24

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Sean M. Gulley ,  James D. Guilford

    IPC: G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  H03M7/30

    CPC classification number: H03M7/3086 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0673 ,  G06F9/3818 ,  G06F9/3863 ,  G06F12/023 ,  G06F12/0875 ,  G06F2212/1044 ,  G06F2212/452 ,  H03M7/3091 ,  H03M7/6005 ,  H03M7/6017

    Abstract: Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.

    Abstract translation: 用于数据解压缩的技术包括从输入流读取符号标记字节的计算设备。 计算设备确定是否可以使用快速路径例程来解码符号，如果不是，则执行慢路径例程来解压缩符号。 慢路径例程可以包括使用分支预测硬件可能不可预测的依赖于数据的分支指令。 对于快速路径例程，计算设备基于标签字节确定下一个符号递增值，文字增量值，数据长度和偏移量，而不执行不可预测的分支指令。 计算设备将源指针设置为文字数据或引用数据作为标记字节的函数，而不执行不可预测的分支指令。 计算设备可以使用条件移动指令来设置源指针。 计算设备复制数据并处理剩余符号。 描述和要求保护其他实施例。

    Generating multiple secure hashes from a single data buffer
    122.
    发明授权
    Generating multiple secure hashes from a single data buffer 有权
    从单个数据缓冲区生成多个安全散列

    公开(公告)号：US09425953B2

    公开(公告)日：2016-08-23

    申请号：US14050326

    申请日：2013-10-09

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Vinodh Gopal ,  Wajdi K. Feghali ,  James D. Guilford ,  Gilbert M. Wolrich ,  Kirk S. Yap

    IPC: H04L9/06

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F21/72 ,  H04L9/3242 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/20

    Abstract: One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.

    Abstract translation: 一个实施例提供了一种装置。 该装置包括单个指令多数据（SIMD）散列模块，其被配置为将长度为L的消息的至少第一部分分配给数量（S）个段，该消息包括多个数据元素序列，每个序列包括 S个数据元素，分配给相应段的每个序列中的相应数据元素，每个段包括N个数据元素块，并且并行地对S个段进行散列，导致S段摘要，基于S个散列摘要 至少部分地在初始值上存储S哈希摘要; 填充模块，被配置为填补余数，剩余部分对应于消息的第二部分，与消息的长度L相关的第二部分，段的数量和块大小; 以及非SIMD散列模块，被配置为对填充的余数进行散列，产生附加的散列摘要并存储附加散列摘要。

    INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS
    123.
    发明申请
    INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS 有权
    指令处理器，方法和系统来处理安全的哈希算法

    公开(公告)号：US20160162694A1

    公开(公告)日：2016-06-09

    申请号：US15011902

    申请日：2016-02-01

    Applicant: INTEL CORPORATION

    Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford

    IPC: G06F21/60 ,  G06F9/30

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F21/602 ,  G06F21/64 ,  G06F21/72

    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

    Abstract translation: 方面的方法包括接收指令。 该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。 该指令指示第二打包数据的第二来源。 第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。 该方法还包括响应于指令将结果存储在由指令指示的目的地中。 结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

    Architecture and instruction set for implementing advanced encryption standard (AES)
    125.
    发明授权
    Architecture and instruction set for implementing advanced encryption standard (AES) 有权
    实现高级加密标准（AES）的体系结构和指令集

    公开(公告)号：US09230120B2

    公开(公告)日：2016-01-05

    申请号：US14100970

    申请日：2013-12-09

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    IPC: G06F21/00 ,  G06F21/60 ,  H04L9/06

    CPC classification number: H04L9/0631 ,  G06F9/30007 ,  G06F21/602 ,  H04L9/14 ,  H04L2209/24

    Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

    Abstract translation: 提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。 提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。 除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

    Managing state in accelerators
    130.
    发明授权
    Managing state in accelerators 有权

    公开(公告)号：US12052370B2

    公开(公告)日：2024-07-30

    申请号：US16865492

    申请日：2020-05-04

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal

    IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08 ,  H04L9/40 ,  H04L67/1001

    CPC classification number: H04L9/3242 ,  H04L9/0631 ,  H04L9/0825 ,  H04L9/3268 ,  H04L63/123 ,  H04L67/1001 ,  H04L2209/122

    Abstract: Methods and apparatus for managing state in accelerators. An accelerator performs processing operations on a data chunk relating to a job submitted to the accelerator. During or following processing the data chunk, the accelerator generates state information corresponding to its current state and stores the state information or, optionally, the accelerator state information is obtained and stored by privileged software. In connection with continued processing of the current data chunk or a next job and next data chunk, the accelerator accesses previously stored state information identified by the job and validates the state information was generated by itself, another accelerator, or privileged software. Valid state information is then reloaded to restore the state of the accelerator/process state, and processing continues. The chunk processing, accelerator state store, validation, and restore operations are repeated to process subsequent jobs. An accelerator and/or privileged software may use a MAC (Message Authentication Code) algorithm to generate a MAC over a message comprising the accelerator state information. The MAC is then used to validate previously stored state information.

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