公开(公告)号：US07342277B2

公开(公告)日：2008-03-11

申请号：US11285763

申请日：2005-11-21

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L29/76

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

公开(公告)号：US20070126067A1

公开(公告)日：2007-06-07

申请号：US11293753

申请日：2005-12-01

申请人： Michael Hattendorf ,  Justin Brask ,  Justin Sandford ,  Jack Kavalieros ,  Matthew Metz

发明人： Michael Hattendorf ,  Justin Brask ,  Justin Sandford ,  Jack Kavalieros ,  Matthew Metz

IPC分类号： H01L21/338 ,  H01L29/94

CPC分类号： H01L21/28114 ,  H01L21/26586 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.

摘要翻译： 本发明的实施例提供一种具有反向锥形栅极电极和栅极电介质层的器件，其长度接近栅极长度。 在一个实施例中，这可以通过用一个或多个成角度的离子注入来改变覆盖介电层的部分，然后去除覆盖介电层的改变的部分来完成。

公开(公告)号：US20070114593A1

公开(公告)日：2007-05-24

申请号：US11285763

申请日：2005-11-21

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

摘要翻译： 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

公开(公告)号：US20080151603A1

公开(公告)日：2008-06-26

申请号：US12072971

申请日：2008-02-28

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC分类号： G11C11/34

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

摘要翻译： 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

公开(公告)号：US20060237804A1

公开(公告)日：2006-10-26

申请号：US11473459

申请日：2006-06-22

申请人： Robert Chau ,  Justin Brask ,  Chris Barns ,  Scott Hareland

发明人： Robert Chau ,  Justin Brask ,  Chris Barns ,  Scott Hareland

IPC分类号： H01L29/772 ,  H01L21/4763

CPC分类号： H01L29/66545 ,  H01L29/7842

摘要： The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.

摘要翻译： 本发明涉及在晶体管结构之上沉积一层，引起晶体管内的晶体应力，并导致性能的提高。 应力层可以形成在形成在衬底上或多个选定晶体管上方的多个晶体管的上方。

公开(公告)号：US20050026451A1

公开(公告)日：2005-02-03

申请号：US10632470

申请日：2003-08-01

申请人： Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

发明人： Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

IPC分类号： H01L21/3063 ,  H01L21/28 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/28123 ,  H01L21/31111

摘要： A high-K thin film patterning solution is disclosed to address structural and process limitations of conventional patterning techniques. Subsequent to formation of gate structures adjacent a high-K dielectric layer, a portion of the high-K dielectric layer material is reduced, preferably via exposure to hydrogen gas, to form a reduced portion of the high-K dielectric layer. The reduced portion may be selectively removed utilizing wet etch chemistries to leave behind a trench of desirable geometric properties.

摘要翻译： 公开了一种高K薄膜图形解决方案，以解决常规图案化技术的结构和工艺限制。 在与高K电介质层相邻形成栅极结构之后，优选通过暴露于氢气来降低高K电介质层材料的一部分，以形成高K电介质层的减少的部分。 可以使用湿蚀刻化学物质选择性地去除还原部分，以留下所需几何性质的沟槽。

公开(公告)号：US20050145894A1

公开(公告)日：2005-07-07

申请号：US10749196

申请日：2003-12-30

申请人： Robert Chau ,  Justin Brask ,  Chris Barns ,  Scott Hareland

发明人： Robert Chau ,  Justin Brask ,  Chris Barns ,  Scott Hareland

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L21/8234 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/66545 ,  H01L29/7842

摘要： The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.

摘要翻译： 本发明涉及在晶体管结构之上沉积一层，引起晶体管内的晶体应力，并导致性能的提高。 应力层可以形成在形成在衬底上或多个选定晶体管上方的多个晶体管的上方。

公开(公告)号：US20050266692A1

公开(公告)日：2005-12-01

申请号：US10859328

申请日：2004-06-01

申请人： Justin Brask ,  Brian Doyle ,  Uday Shah ,  Robert Chau

发明人： Justin Brask ,  Brian Doyle ,  Uday Shah ,  Robert Chau

IPC分类号： H01L21/302 ,  H01L21/308 ,  H01L21/311 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/31111 ,  H01L21/3081 ,  H01L21/76838 ,  H01L29/785

摘要： A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of laterally opposite sidewalls. Next, the mask is removed from above the patterned film. After removing the mask from the patterned film, the protective layer is removed from the sidewalls.

摘要翻译： 图案化薄膜的方法。 该方法包括在待图案化的膜上形成掩模。 然后将膜与掩模对准地蚀刻以形成具有一对横向相对的侧壁的图案化膜。 在一对横向相对的侧壁上形成保护层。 接下来，从图案化膜的上方去除掩模。 在从图案化的膜去除掩模之后，从侧壁去除保护层。

公开(公告)号：US20060214231A1

公开(公告)日：2006-09-28

申请号：US11440313

申请日：2006-05-23

申请人： Uday Shah ,  Brian Doyle ,  Justin Brask ,  Robert Chau ,  Thomas Letson

发明人： Uday Shah ,  Brian Doyle ,  Justin Brask ,  Robert Chau ,  Thomas Letson

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20050110072A1

公开(公告)日：2005-05-26

申请号：US11018015

申请日：2004-12-20

申请人： Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

发明人： Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

IPC分类号： H01L21/3063 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/28123 ,  H01L21/31111

摘要： A high-K thin film patterning solution is disclosed to address structural and process limitations of conventional patterning techniques. Subsequent to formation of gate structures adjacent a high-K dielectric layer, a portion of the high-K dielectric layer material is reduced, preferably via exposure to hydrogen gas, to form a reduced portion of the high-K dielectric layer. The reduced portion may be selectively removed utilizing wet etch chemistries to leave behind a trench of desirable geometric properties.