公开(公告)号：US20250131973A1

公开(公告)日：2025-04-24

申请号：US18790365

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Mark Kalei Hadrick ,  Kang-Yong Kim ,  Donald Morgan ,  Victor Wong

IPC: G11C29/44 ,  G11C29/30 ,  G11C29/36

Abstract: Apparatuses and techniques for logging a memory address associated with faulty usage-based disturbance data are described. In an example aspect, a memory device can detect, at a local-bank level, a fault associated with usage-based disturbance data. This detection enables the memory device to log a row address associated with the faulty usage-based disturbance data. To avoid increasing a complexity and/or a size of the memory device, some implementations of the memory device can perform the address logging at the multi-bank level with the assistance of an engine, such as a test engine. The memory device stores the logged address in at least one mode register to communicate the fault to a memory controller. With the logged address, the memory controller can initiate a repair procedure to fix the faulty usage-based disturbance data.

公开(公告)号：US20250118353A1

公开(公告)日：2025-04-10

申请号：US18746473

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Song Guo ,  Yuan He ,  Kang-Yong Kim

IPC: G11C11/4091 ,  G11C5/06 ,  G11C11/4097

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

公开(公告)号：US20250118352A1

公开(公告)日：2025-04-10

申请号：US18746447

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Toby D. Robbs ,  Christopher J. Kawamura ,  Kang-Yong Kim

IPC: G11C11/4091 ,  G11C5/06 ,  G11C11/4097

Abstract: Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

公开(公告)号：US20250095699A1

公开(公告)日：2025-03-20

申请号：US18962783

申请日：2024-11-27

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Taeksang Song

IPC: G11C7/10 ,  G11C8/06 ,  G11C11/4074

Abstract: Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

公开(公告)号：US12229062B2

公开(公告)日：2025-02-18

申请号：US17823432

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Creston M. Dupree ,  Kang-Yong Kim

IPC: G06F13/16 ,  G06F11/07

Abstract: Described apparatuses and methods relate to erroneous select die access (SDA) detection for a memory system. A memory system may include a memory controller and a memory device that are capable of implementing an SDA protocol that enables selective memory die access to multiple memory devices that couple to a command bus. A memory device can include logic that determines if signaling that conflicts with the SDA protocol is detected. If it is determined that conflicting signaling is detected, the logic may provide an indication of the conflicted signaling. In doing so, the erroneous SDA detection described herein may reduce the likelihood of a memory device erroneously masking memory dice, thereby limiting the memory device from exhibiting unexpected, and in some cases, dangerous behavior.

公开(公告)号：US12197733B2

公开(公告)日：2025-01-14

申请号：US17965957

申请日：2022-10-14

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to memory system refresh management are described herein. In an example, a refresh operation can be performed on a set of memory cells in a memory device. The memory device comprising a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The refresh operation can include receiving a mode register write command. The refresh operation can include writing mode register data associated with the mode register write command. The refresh operation can be performed on the set of memory cells at an address location indicated by the written mode register data.

公开(公告)号：US12197355B2

公开(公告)日：2025-01-14

申请号：US17751298

申请日：2022-05-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20240371426A1

公开(公告)日：2024-11-07

申请号：US18635631

申请日：2024-04-15

Applicant: Micron Technology, Inc.

Inventor： Yunyoung Lee ,  Yuan He ,  Yang Lu ,  Kang-Yong Kim

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/4096

Abstract: Apparatuses and techniques for implementing bank-shared usage-based disturbance circuitry are described. Bank-shared usage-based disturbance circuitry is coupled to the at least two banks of a memory device and can mitigate usage-based disturbance within these banks. To detect a condition associated with usage-based disturbance, the bank-shared usage-based disturbance circuitry selectively reads data associated with usage-based disturbance from one of the at least two banks. To mitigate usage-based disturbance, the bank-shared usage-based disturbance circuitry can selectively cause one or more rows within either of the at least two banks to be refreshed. By using the same circuitry to mitigate usage-based disturbance across multiple banks, the total footprint, complexity, and power consumption of the memory device can be reduced relative to other memory devices that utilize circuitry that is dedicated for each bank. Consequently, the memory device can be integrated within space-constrained and power-constrained devices such as, for example, portable devices.

公开(公告)号：US20240347100A1

公开(公告)日：2024-10-17

申请号：US18629445

申请日：2024-04-08

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Yang Lu ,  Dong Pan ,  Kang-Yong Kim

IPC: G11C11/4076 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C11/40622 ,  G11C11/4085

Abstract: A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.

公开(公告)号：US20240347096A1

公开(公告)日：2024-10-17

申请号：US18628127

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Mark Kalei Hadrick ,  HyunYoo Lee ,  KeunSoo Song ,  John Christopher Sancon ,  Kang-Yong Kim

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/4096

Abstract: Apparatuses and techniques for implementing usage-based disturbance counter clearance are described. In example implementations, a memory device includes a memory array having multiple rows. The memory device also includes multiple usage-based disturbance counters that are associated with the memory array. The memory device further includes logic that performs a refresh operation on a row of the multiple rows responsive to a refresh command. The logic also clears a usage-based disturbance counter of the multiple usage-based disturbance counters responsive to the refresh command. Here, the usage-based disturbance counter stores a quantity of accesses to the row of the multiple rows. This can reduce a frequency of performing usage-based disturbance mitigation procedures that would otherwise be applied to the multiple usage-based disturbance counters, thereby saving power and avoiding denial-of-service periods with the memory array.