公开(公告)号：US08389365B2

公开(公告)日：2013-03-05

申请号：US13077501

申请日：2011-03-31

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/11536 ,  H01L29/66825

摘要： A method for forming an integrated circuit for a non-volatile memory cell transistor is disclosed that includes: forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate; forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region; forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region; and removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region. After the removing, a second layer of barrier work function material is formed over the substrate in the first region and the second region. The second layer of barrier work function material is removed from the first region. A first gate of a memory device is formed in the first region. The first gate includes a portion of the first layer of barrier work function material. The memory device includes a charge storage structure including a portion of the layer of discrete storage elements. A second gate of a transistor is formed in the second region, the second gate including a portion of the second layer of barrier work function material.

摘要翻译： 公开了一种用于形成用于非易失性存储单元晶体管的集成电路的方法，其包括：在所述衬底的第一区域和所述衬底的第二区域中的衬底上形成离散存储元件层; 在所述第一区域和所述第二区域中的离散存储元件层上形成第一介电材料层; 在所述第一区域和所述第二区域中的所述第一介电材料层上形成阻挡功函数材料的第一层; 以及从所述第二区域去除所述第一层屏障功能材料，从所述第二区域去除所述第一介电材料层，以及从所述第二区域移除所述离散存储元件层。 在去除之后，在第一区域和第二区域中的衬底上形成第二层屏障功能材料层。 从第一区域去除第二层屏障功能材料。 存储器件的第一栅极形成在第一区域中。 第一栅极包括第一层屏障功能材料的一部分。 存储器件包括电荷存储结构，其包括离散存储元件层的一部分。 晶体管的第二栅极形成在第二区域中，第二栅极包括第二层屏障功能材料的一部分。

公开(公告)号：US20130055184A1

公开(公告)日：2013-02-28

申请号：US13216769

申请日：2011-08-24

申请人： Mehul D. Shroff ,  Ertugrul Demircan

发明人： Mehul D. Shroff ,  Ertugrul Demircan

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer.

摘要翻译： 数据处理系统确定与包括在设备设计中的节点相对应的当前信息。 接收对应于节点的物理布局信息，物理布局信息包括一个或多个布局几何形状，一个或多个布局几何形状提供电路网络。 电路网络可以被划分成两个或更多个网段。 基于当前信息，识别在网段进行的电流。 接收代表包括在网段中的布局几何尺寸和金属层的信息。 计算机确定电流超过预定的最大阈值，基于尺寸和金属层确定的预定最大阈值。

公开(公告)号：US08318576B2

公开(公告)日：2012-11-27

申请号：US13092046

申请日：2011-04-21

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/20

CPC分类号： H01L29/945 ,  H01L27/0629 ,  H01L29/66181

摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.

摘要翻译： 一种半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层中的底部电容器板，覆盖的电容器电介质层和凹陷顶部电容器板 通过STI区域并且通过侧壁电介质层与串扰隔离。

公开(公告)号：US20120267759A1

公开(公告)日：2012-10-25

申请号：US13092046

申请日：2011-04-21

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L27/0629 ,  H01L29/66181

摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.

摘要翻译： 一种半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层中的底部电容器板，覆盖的电容器电介质层和凹陷顶部电容器板 通过STI区域并且通过侧壁电介质层与串扰隔离。

公开(公告)号：US20120267758A1

公开(公告)日：2012-10-25

申请号：US13092037

申请日：2011-04-21

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer (10) below a trench opening, a capacitor dielectric layer (22) and a recessed top capacitor plate (28) that is covered by an STI region (30) and isolated from cross talk by a sidewall dielectric layer (23).

摘要翻译： 半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层（10）中的底部电容器板，电容器电介质层（22）和凹陷 顶部电容器板（28），其被STI区域（30）覆盖并且由侧壁电介质层（23）与串扰隔离。

公开(公告)号：US20120252178A1

公开(公告)日：2012-10-04

申请号：US13077563

申请日：2011-03-31

申请人： Bradley P. Smith ,  Mehul D. Shroff

发明人： Bradley P. Smith ,  Mehul D. Shroff

IPC分类号： H01L21/8239 ,  H01L21/20

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L28/60

摘要： A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region.

摘要翻译： 电容器和NVM单元以集成的方式形成，使得电容器的蚀刻在对NVM单元的蚀刻的端点检测中是有用的。 这是通过在NVM区域上和电容器区域上的两个导电层来实现的。 对第一导电层进行图案化以制备随后的图案化步骤，其包括在NVM区域和电容器区域中图案化第一导电层和第二导电层的步骤。 随后的蚀刻通过使用相同的掩模蚀刻两个导电层来提供浮动栅极与上覆控制栅极的重要对准。 在该随后的蚀刻期间，在电容器区域中蚀刻第一导电材料的事实有助于终端检测NVM区域中的第一导电层的蚀刻。

公开(公告)号：US08202778B2

公开(公告)日：2012-06-19

申请号：US12872073

申请日：2010-08-31

申请人： Mehul D. Shroff

发明人： Mehul D. Shroff

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11534 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332

摘要： Forming a gate stack of a non-volatile memory (NVM) over a substrate having an NVM region and non-NVM region which does not overlap the NVM region includes forming a select gate layer over the substrate in the NVM and non-NVM regions; simultaneously etching the select gate layer in the NVM and non-NVM regions; forming a charge storage layer over the substrate in the NVM and non-NVM regions; forming a control gate layer over the charge storage layer in the NVM and non-NVM regions; and simultaneously etching the charge storage layer in the NVM and the non-NVM regions. Etching the select gate layer in the NVM region results in a portion of the charge storage layer over a portion of the select gate layer and overlapping a sidewall of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer.

摘要翻译： 在具有不与NVM区域重叠的NVM区域和非NVM区域的衬底上形成非易失性存储器（NVM）的栅极堆叠包括在NVM和非NVM区域中的衬底上形成选择栅极层; 同时蚀刻NVM和非NVM区域中的选择栅极层; 在NVM和非NVM区域中的衬底上形成电荷存储层; 在NVM和非NVM区域中的电荷存储层上形成控制栅极层; 同时蚀刻NVM和非NVM区域中的电荷存储层。 蚀刻NVM区域中的选择栅极层导致电荷存储层的一部分在选择栅极层的一部分上并且与选择栅极层的侧壁重叠，并导致控制栅极层的部分在 电荷存储层。

公开(公告)号：US07951695B2

公开(公告)日：2011-05-31

申请号：US12125856

申请日：2008-05-22

申请人： David M. Schraub ,  Terry A. Breeden ,  James D. Legg ,  Mehul D. Shroff ,  Ruiqi Tian

发明人： David M. Schraub ,  Terry A. Breeden ,  James D. Legg ,  Mehul D. Shroff ,  Ruiqi Tian

IPC分类号： H01L21/26 ,  H01L21/42

CPC分类号： H01L21/26513 ,  H01L21/0271 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/088

摘要： A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist (114) which includes resist openings formed (117) over the active circuit areas (13, 14) as well as additional resist openings (119) formed over inactive areas (15) in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings (119) are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures (e.g., 152) for use in manufacturing the final structure.

摘要翻译： 一种半导体工艺和装置，用于通过施加包括在有源电路区域（13,14）上形成的抗蚀剂开口（117）的光致抗蚀剂（114）的图案化层以及附加的抗蚀剂开口（114）来提供减少等离子体引起的损伤的方法 119），以便保持阈值覆盖水平以控制半导体结构上的抗蚀剂覆盖的量，使得抗蚀剂覆盖的总量处于或低于阈值覆盖水平。 为了保持阈值覆盖水平，需要额外的抗蚀剂开口（119），这些开口可用于产生用于制造最终结构的附加电荷耗散结构（例如，152）。

公开(公告)号：US07843011B2

公开(公告)日：2010-11-30

申请号：US11669794

申请日：2007-01-31

申请人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

发明人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US07741221B2

公开(公告)日：2010-06-22

申请号：US11302769

申请日：2005-12-14

申请人： Ruiqi Tian ,  Willard E. Conley ,  Mehul D. Shroff

发明人： Ruiqi Tian ,  Willard E. Conley ,  Mehul D. Shroff

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0334 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/32139 ,  Y10S438/926

摘要： A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.

摘要翻译： 一种用于形成半导体器件的方法包括在布局中提供多个特征，从多个特征中选择关键特征，将布置中的第一多个短距离虚拟蚀刻特征放置在离关键特征的第一距离处以增加 临界特征附近的特征密度，其中第一多个短距离虚拟蚀刻特征中的每一个具有第一宽度，从布局去除第一多个短程虚拟蚀刻特征中的至少一个，随后将干扰 至少一个有源特征的电性能，使得第二多个短距离虚拟蚀刻特征保留，并且使用布局来在半导体衬底上图案化。