公开(公告)号：US20080099231A1

公开(公告)日：2008-05-01

申请号：US11829974

申请日：2007-07-30

Applicant: LIANG-YAO CHANG ,  SHOU-KUO HSU

Inventor： LIANG-YAO CHANG ,  SHOU-KUO HSU

IPC: H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/162 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09618 ,  H05K2201/09663

Abstract: An exemplary printed circuit board includes a power plane, and a ground plane. The power plane includes two power modules, and a strip made of insulating medium disposed between the two power modules for insulating the two power modules from each other. The ground plane is insulated from the power plane, a plurality of vias electrically connects the power plane and the ground plane, and is close to the strip. Each via is insulated from the power module by an annular insulating medium. Each power module and the vias forms an equivalent coupling capacitance, and SSN can be conducted to the ground plane via the equivalent coupling capacitance, therefore, the SSN in the PCB is suppressed.

Abstract translation: 示例性印刷电路板包括电源平面和接地平面。 电力平面包括两个电源模块，以及由两个电源模块之间的绝缘介质制成的条，用于将两个电源模块彼此隔离。 接地层与电源平面绝缘，多个通孔将电源平面和接地平面电连接，并且靠近条带。 每个通孔都通过环形绝缘介质与电源模块绝缘。 每个电源模块和通孔形成等效的耦合电容，SSN可以通过等效耦合电容传导到接地层，因此PCB中的SSN被抑制。

公开(公告)号：US20080052020A1

公开(公告)日：2008-02-28

申请号：US11768923

申请日：2007-06-27

Applicant: SHOU-KUO HSU ,  CHUN-SHAN HSIAO

Inventor： SHOU-KUO HSU ,  CHUN-SHAN HSIAO

IPC: G06F19/00

CPC classification number: G06F17/5081

Abstract: A system for checking a reference plane of a signal trace in a PCB includes: a database, a signal filter, a signal trace selecting unit, a reference plane checking unit and a display unit. The database is configured for storing a plurality of signal files. The signal file in the PCB constitutes one or more signal groups. Each signal group has a same bus. The signal filter is configured for filtering a signal group from a signal file. The signal trace selecting unit is configured for selecting a signal for checking, from the signal group, and for selecting a trace corresponding to the signal. The reference plane checking unit is configured for checking the integrity of a reference plane that is nearest to the selected signal trace through orthographically projecting the selected signal trace to the reference plane and for checking a relationship between the reference plane and the projection. A related method is also disclosed.

Abstract translation: 用于检查PCB中的信号迹线的参考平面的系统包括：数据库，信号滤波器，信号轨迹选择单元，参考平面检查单元和显示单元。 数据库被配置为存储多个信号文件。 PCB中的信号文件构成一个或多个信号组。 每个信号组具有相同的总线。 信号滤波器被配置为从信号文件中滤波信号组。 信号跟踪选择单元被配置为从信号组中选择用于检查信号的信号，并且用于选择对应于该信号的迹线。 参考平面检查单元被配置为通过将所选择的信号迹线正交投影到参考平面并且用于检查参考平面和投影之间的关系来检查最接近所选择的信号迹线的参考平面的完整性。 还公开了相关方法。

公开(公告)号：US20080023221A1

公开(公告)日：2008-01-31

申请号：US11565651

申请日：2006-12-01

Applicant: SHOU-KUO HSU ,  YU-CHANG PAI ,  CHENG-HONG LIU

Inventor： SHOU-KUO HSU ,  YU-CHANG PAI ,  CHENG-HONG LIU

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/116 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: An exemplary printed circuit board includes at least a pair of differential vias defined therein, each of the differential vias has an annular ring formed on the PCB, a conductive hole defined in the PCB, and a clearance hole defined in at least one inner layer of the PCB. Each of the clearance holes of the differential vias is oval shaped thus providing a greater area for the clearance holes and needed clearance between vias without creating a superposition zone.

Abstract translation: 示例性印刷电路板包括限定在其中的至少一对差分通孔，每个差分通孔具有形成在PCB上的环形圈，限定在PCB中的导电孔，以及限定在至少一个内层中的间隙孔 PCB。 差动通孔的每个间隙孔都是椭圆形的，从而为间隙孔提供了更大的面积，并且在通道之间需要间隙而不产生叠加区域。

公开(公告)号：US20080010622A1

公开(公告)日：2008-01-10

申请号：US11615008

申请日：2006-12-22

Applicant: SHOU-KUO HSU ,  CHENG-SHIEN LI

Inventor： SHOU-KUO HSU ,  CHENG-SHIEN LI

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/504

Abstract: A method for analyzing response values sum of differential signals includes: receiving configurations of simulation parameters; simulating differential signal paths with an analog transmission channel according to a design file; analyzing the analog transmission channel into different channel modes according to received configurations; simulating a plurality of pulse signals into the analog transmission channel according to the received configurations, and recording an impulse response of each of the channel modes; simulating differential signal transmissions of the differential signals according to the received configurations, and analyzing the differential signal transmissions into different signal modes corresponding to the different channel modes; transforming each signal mode and the impulse response of a corresponding channel mode to respectively generate a first value and a second value by utilizing Fast Fourier Transform Algorithm; multiplying the first value by the second value to generate a third value, and transforming the third value to a fourth value by utilizing an Inverse Fast Fourier Transform Algorithm; and summing all the fourth values corresponding to all of the channel modes to be the response values sum of the differential signals. A related system is also disclosed.

Abstract translation: 用于分析差分信号的响应值和的方法包括：接收模拟参数的配置; 根据设计文件用模拟传输通道模拟差分信号路径; 根据接收的配置，将模拟传输信道分析成不同的信道模式; 根据接收到的配置将多个脉冲信号模拟成模拟传输信道，并记录每个信道模式的脉冲响应; 根据接收到的配置模拟差分信号的差分信号传输，并将差分信号传输分析成对应于不同信道模式的不同信号模式; 通过利用快速傅立叶变换算法来变换每个信号模式和相应信道模式的脉冲响应，分别产生第一值和第二值; 将第一值乘以第二值以产生第三值，并且通过利用快速傅里叶逆变换算法将第三值变换为第四值; 并将与所有信道模式相对应的所有第四值求和作为差分信号的响应值和。 还公开了相关系统。

公开(公告)号：US20070233408A1

公开(公告)日：2007-10-04

申请号：US11627378

申请日：2007-01-26

Applicant: DUEN-YI HO ,  SHOU-KUO HSU

Inventor： DUEN-YI HO ,  SHOU-KUO HSU

IPC: G01R13/00 ,  H03K5/153 ,  G06F15/00

CPC classification number: G06F17/5036

Abstract: A method for calculating a voltage spike value includes: predefining calculating requirements; inputting parameter values; analyzing whether inputted parameter values match with the calculating requirements; establishing a computing formula for calculating the voltage spike value if the inputted parameter values match with the calculating requirements; and calculating the voltage spike value by utilizing the inputted parameter values and the computing formula. A related system is also disclosed.

Abstract translation: 计算电压尖峰值的方法包括：预定义计算要求; 输入参数值; 分析输入的参数值是否符合计算要求; 如果输入的参数值与计算要求匹配，建立计算公式计算电压尖峰值; 以及通过利用输入的参数值和计算公式计算电压尖峰值。 还公开了相关系统。

公开(公告)号：US20070170971A1

公开(公告)日：2007-07-26

申请号：US11309216

申请日：2006-07-13

Applicant: YING-TSO LAI ,  SHOU-KUO HSU

Inventor： YING-TSO LAI ,  SHOU-KUO HSU

IPC: H03K5/08

CPC classification number: H03K5/15046 ,  H04L25/0278 ,  H04L25/08

Abstract: A signal transmitting circuit includes a driving circuit, and a plurality of receiving circuits receiving signals transmitted from the driving circuit. Each of the receiving circuits is coupled to the driving circuit consecutively via a transmission line. A filter means is coupled with a segment of the transmission line of two neighboring receiving circuits for filtering signal reflections from the receiving circuits.

Abstract translation: 信号发送电路包括驱动电路和接收从驱动电路发送的信号的多个接收电路。 每个接收电路经由传输线连续地连接到驱动电路。 滤波器装置与两个相邻接收电路的传输线的一段相耦合，用于滤波来自接收电路的信号反射。

公开(公告)号：US20060291547A1

公开(公告)日：2006-12-28

申请号：US11308933

申请日：2006-05-29

Applicant: SHOU-KUO HSU

Inventor： SHOU-KUO HSU

IPC: H04B3/46

CPC classification number: G06F13/4226

Abstract: A device and a method for testing signal-receiving sensitivity of an electronic subassembly are provided. The device includes a control board and a computer. The control board is connected to the electronic subassembly. The computer is connected to the control board and also connected to the electronic subassembly. Wherein signals sent by the computer are compared with signals received by the computer for adjusting predetermined parameters associated with the signal-receiving sensitivity.

Abstract translation: 提供了一种用于测试电子组件的信号接收灵敏度的装置和方法。 该设备包括控制板和计算机。 控制板连接到电子组件。 计算机连接到控制板，并连接到电子组件。 其中计算机发送的信号与计算机接收的信号进行比较，以调整与信号接收灵敏度相关联的预定参数。

公开(公告)号：US20120331437A1

公开(公告)日：2012-12-27

申请号：US13407768

申请日：2012-02-29

Applicant: CHIA-NAN PAI ,  SHOU-KUO HSU ,  YA-LING HUANG

Inventor： CHIA-NAN PAI ,  SHOU-KUO HSU ,  YA-LING HUANG

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.

Abstract translation: 在使用电子设备检查印刷电路板（PCB）的布局的方法中，从PCB的布局图中选择信号线。 该方法搜索在PCB布局图中偏离直线时具有锐角的信号线。 该方法进一步在PCB的布局图中定位搜索到的信号线的属性数据，并将所搜索的信号线的属性数据显示在电子设备的显示装置上。

公开(公告)号：US20120247825A1

公开(公告)日：2012-10-04

申请号：US13288144

申请日：2011-11-03

Applicant: MING WEI ,  CHIA-NAN PAI ,  NING LI ,  SHOU-KUO HSU

Inventor： MING WEI ,  CHIA-NAN PAI ,  NING LI ,  SHOU-KUO HSU

IPC: H05K1/11

CPC classification number: H05K1/0222 ,  H05K1/0245 ,  H05K2201/09618

Abstract: A printed circuit board (PCB) includes a top signal layer, a bottom signal layer, a ground layer, a plurality of vias, and at least two ground vias. Both the top signal layer and the bottom signal layer include at least one protection line. The ground layer is located between the top signal layer and the bottom signal layer. The at least two ground vias extend through the PCB and are located adjacent to the vias on the PCB. The at least two ground vias are electrically connected to the ground layer to conduct noise signals, and the at least two ground vias are electrically connected by the protection lines to insulate noise signals.

Abstract translation: 印刷电路板（PCB）包括顶部信号层，底部信号层，接地层，多个通孔和至少两个接地通孔。 顶部信号层和底部信号层都包括至少一个保护线。 接地层位于顶层信号层和底层信号层之间。 至少两个接地通孔延伸穿过PCB，并且位于邻近PCB上的通孔处。 所述至少两个接地通孔电连接到接地层以传导噪声信号，并且所述至少两个接地通孔由保护线电连接以绝缘噪声信号。

公开(公告)号：US20120241201A1

公开(公告)日：2012-09-27

申请号：US13107950

申请日：2011-05-15

Applicant: HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: H05K1/09

CPC classification number: H05K1/025 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/09727

Abstract: A circuit board includes a substrate and a copper layer positioned on the substrate. The copper layer includes a BGA area and a non-BGA area, and includes traces. The widths of the traces in the BGA area are smaller than the widths of the traces in the non-BGA area, the dielectric coefficient of the substrate in the BGA area is greater than the dielectric coefficient of the substrate in the non-BGA area for keeping the impedance of the traces consistent in the BGA area and in the non-BGA area.

Abstract translation: 电路板包括基板和位于基板上的铜层。 铜层包括BGA区域和非BGA区域，并且包括痕迹。 BGA区域中的迹线的宽度小于非BGA区域中的迹线的宽度，BGA区域中的衬底的介电系数大于非BGA区域中衬底的介电系数， 保持BGA区域和非BGA区域的轨迹阻抗一致。