公开(公告)号：US20140246720A1

公开(公告)日：2014-09-04

申请号：US14194345

申请日：2014-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L27/115 ,  H01L21/8234

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/7881

Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.

Abstract translation: 集成电路形成在半导体衬底上，并且包括沟槽导体和形成在衬底表面上的第一晶体管。 晶体管包括：晶体管栅极结构，在栅极结构的第一边缘和沟槽导体的上边缘之间的衬底中延伸的第一掺杂区域和形成在栅极结构的第一边缘上方的第一间隔区， 第一掺杂区域。 第一间隔物完全覆盖第一掺杂区域，并且硅化物存在于沟槽导体上，但不存在于第一掺杂区域的表面上。

公开(公告)号：US08809858B2

公开(公告)日：2014-08-19

申请号：US13750790

申请日：2013-01-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Thierry Soudé ,  Alexandre Sarafianos ,  Francesco La Rosa

IPC: H01L29/40

CPC classification number: H01L23/57 ,  G06F21/87 ,  H01L21/22 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit including: a semiconductor substrate of a first conductivity type having at least one well of a second conductivity type laterally delimited, on two opposite walls, by regions of the first conductivity type, defined at its surface; at least one region of the second conductivity type which extends in the semiconductor substrate under the well; and a system for detecting a variation of the substrate resistance between each association of two adjacent regions of the first conductivity type.

Abstract translation: 一种集成电路，包括：第一导电类型的半导体衬底，其具有在其两个相对的壁上由其表面限定的第一导电类型的区域侧向界定的第二导电类型的至少一个阱; 所述第二导电类型的至少一个区域在所述阱下面的所述半导体衬底中延伸; 以及用于检测第一导电类型的两个相邻区域的每个缔合之间的衬底电阻的变化的系统。

公开(公告)号：US20140191291A1

公开(公告)日：2014-07-10

申请号：US14148257

申请日：2014-01-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Hélène Dalle-Houilliez

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  G11C16/0433 ,  H01L27/11524 ,  H01L29/66666 ,  H01L29/7827

Abstract: The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.

Abstract translation: 本公开涉及在半导体衬底中制造垂直栅极晶体管的方法，包括在衬底的深度中注入掺杂的隔离层，以形成晶体管的源极区域; 在衬底中形成垂直于沟槽隔离的平行沟槽隔离和第二沟槽，到达隔离层，并通过第一介电层与衬底隔离; 在所述衬底的表面和所述第二沟槽中沉积第一导电层; 蚀刻第一导电层以形成晶体管的垂直栅极，以及在垂直栅极的末端和衬底的边缘之间的垂直栅极连接焊盘，同时在每个连接焊盘和垂直栅极之间的第一导电层中保持连续区域 门; 以及在所述第二沟槽的每一侧上注入掺杂区域，以形成所述晶体管的漏极区域。

公开(公告)号：US20140191179A1

公开(公告)日：2014-07-10

申请号：US14150596

申请日：2014-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2445 ,  H01L27/226 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/04 ,  H01L45/06 ,  H01L45/16

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

Abstract translation: 本公开涉及包括晶体管的集成电路，该晶体管包括第一和第二导电端子以及控制端子。 集成电路还包括第一介电层，导电层和第二介电层的堆叠，第一导电端子包括形成在第一介电层中的第一半导体区域，该控制端子包括形成在第一介电层中的第二半导体区域 导电层，第二导电端子包括形成在第二介电层中的第三半导体区域。

公开(公告)号：US20140097481A1

公开(公告)日：2014-04-10

申请号：US14043718

申请日：2013-10-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Yoann Goasduff

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/788 ,  G11C16/0433 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/4175 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827

Abstract: The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.

Abstract translation: 本公开涉及一种用于在半导体衬底上制造非易失性存储器的方法，包括以下步骤：在衬底的深度中注入形成选择晶体管的源极区的第一掺杂区，在衬底中形成掩埋栅，包括 在衬底的上表面和第一掺杂区之间延伸的深部分，埋入掩埋栅的两个相邻深部之间，形成一对存储单元的公共选择晶体管的公共漏极区的第二掺杂区，选择晶体管 因此具有在第一掺杂区域和第二掺杂区域之间延伸的沟道区域的一对存储单元，沿着与相邻两个深部分的两个掩埋栅极相对的面以及沿掩埋栅极的相对的上边缘注入，形成源极区域的第三掺杂区域 的电荷累积晶体管。

公开(公告)号：US20130063157A1

公开(公告)日：2013-03-14

申请号：US13669741

申请日：2012-11-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G01R27/26

CPC classification number: G01R27/2605 ,  G06F3/0416 ,  G06F3/044

Abstract: The disclosure comprises: linking a first terminal of the capacitance to the mid-point of a first voltage divider bridge, applying a first voltage to a second terminal of the capacitance, maintaining a voltage of a mid-point of the first divider bridge near a reference voltage, and discharging a mid-point of a second divider bridge with a constant current. When a voltage of the mid-point of the second bridge reaches a first voltage threshold, applying a second voltage to the second terminal of the capacitance, and measuring the time for the voltage to reach a second threshold.

Abstract translation: 本公开包括：将电容的第一端子连接到第一分压器桥的中点，将第一电压施加到电容的第二端子，将第一分压器桥的中点的电压保持在 参考电压，并以恒定电流放电第二分频器桥的中点。 当第二桥的中点的电压达到第一电压阈值时，向电容的第二端施加第二电压，并测量电压达到第二阈值的时间。