公开(公告)号：US07154776B2

公开(公告)日：2006-12-26

申请号：US11348359

申请日：2006-02-07

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/14 ,  G11C5/08 ,  G11C7/00 ,  G11C8/00 ,  G11C11/15

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

公开(公告)号：US07116595B2

公开(公告)日：2006-10-03

申请号：US10982895

申请日：2004-11-08

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C7/02

CPC分类号： G11C11/15

摘要： Bit lines and source lines are precharged to a power supply voltage before data read operation. In the data read operation, a corresponding bit line is coupled to a data bus as well as a corresponding source line is driven to a ground voltage only in the selected memory cell column. In the non-selected memory cell columns, the bit lines and the source lines are retained at the precharge voltage, i.e., the power supply voltage. No charging/discharging current is produced in the bit lines of the non-selected memory cell columns, that is, a charging/discharging current that does not directly contribute the data read operation is not produced, thereby allowing for reduction in power consumption in the data read operation.

公开(公告)号：US07020008B2

公开(公告)日：2006-03-28

申请号：US10328032

申请日：2002-12-26

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/00 ,  G11C5/08 ,  G11C11/14 ,  G11C11/15

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

公开(公告)号：US06975147B2

公开(公告)日：2005-12-13

申请号：US10891219

申请日：2004-07-15

申请人： Hideto Hidaka ,  Masakazu Hirose

发明人： Hideto Hidaka ,  Masakazu Hirose

IPC分类号： H03K19/003 ,  H03K3/00

CPC分类号： H03K19/00361

摘要： A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

摘要翻译： 当内部节点的电位达到H电平时，数据输出驱动晶体管导通，从而将输出节点放电到地电位。 当驱动晶体管导通时，输出节点以高速放电到地电位。 当高电平数据的输出完成时，该驱动晶体管导通预定时间段，由此输出节点在预定时间段内被放电到地电位的电平。 结果，输出节点的电位从高电平降低到中间电平，使得后续输出信号的幅度减小。 提供了可以有效地防止产生振铃而不增加访问时间的输出电路。 提供了一种对策，用于当输出节点电位达到不产生振铃的电位时，抑制在输出节点处高速驱动输出节点的振铃。 高速提供稳定的输出信号。

公开(公告)号：US06967862B2

公开(公告)日：2005-11-22

申请号：US10615777

申请日：2003-07-10

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/15 ,  G11C7/00 ,  G11C8/00 ,  G11C11/00 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC分类号： G11C11/16

摘要： In writing data, when a bit line is selected and a data write current is caused to flow the selected bit line, a cancel current for canceling a magnetic field induced by the data write current is caused to flow in the direction opposite to the data write current on the selected bit line through a bit line adjacent to the selected bit line. Magnetic field interference between adjacent memory cells to each other is suppressed in a magnetic semiconductor memory device.

摘要翻译： 在写入数据时，当选择位线并且使数据写入电流流过所选择的位线时，导致用于消除由数据写入电流引起的磁场的消除电流沿与数据写入相反的方向流动 通过与所选位线相邻的位线在选定位线上的电流。 磁性半导体存储器件中抑制相邻存储单元之间的磁场干涉。

公开(公告)号：US20050226042A1

公开(公告)日：2005-10-13

申请号：US11148207

申请日：2005-06-09

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/14 ,  G11C8/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C29/74

摘要： A program unit includes two program cells having an electric resistance varying according to a magnetization direction thereof. These program cells are magnetized in the same direction in initial state, that is, non-program state. In program state, the magnetization direction of one of the program cells selected according to program data is changed from the initial state. One-bit program data and information of whether the program unit stores program data or not can be read based on two program signals generated according to the electric resistances of the two program cells.

摘要翻译： 程序单元包括具有根据其磁化方向而变化的电阻的两个编程单元。 这些程序单元在初始状态，即非程序状态下以相同的方向被磁化。 在程序状态下，根据程序数据选择的一个程序单元的磁化方向从初始状态改变。 可以基于根据两个程序单元的电阻生成的两个程序信号来读取一位程序数据和程序单元是否存储程序数据的信息。

公开(公告)号：US20050219894A1

公开(公告)日：2005-10-06

申请号：US11099669

申请日：2005-04-06

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/15 ,  G11C11/14

CPC分类号： G11C11/16

摘要： After a digit line is charged to a power supply voltage by turn-on of a first switching element, the first switching element is turned off and a second switching element is turned on, whereby the digit line is connected to a ground voltage. Similarly, in order to feed data write current, a bit line is charged to a data voltage in accordance with write data through a third switching element. Then, the bit line is connected to a voltage different from the data voltage by a fourth switching element while the third switching element is turned off. Therefore, a load current from a power supply to an MRAM device is supplied during charging of a digit line capacitance and a bit line capacitance, without being consumed when the data write current flows. Consequently, a peak of the load current supplied from the power supply is suppressed.

摘要翻译： 在通过第一开关元件的接通将数字线充电到电源电压之后，第一开关元件被断开并且第二开关元件导通，从而数字线连接到接地电压。 类似地，为了馈送数据写入电流，根据通过第三开关元件的写入数据将位线充电到数据电压。 然后，第三开关元件断开时，位线被第四开关元件连接到与数据电压不同的电压。 因此，在数字线电容和位线电容的充电期间，从电源到MRAM器件的负载电流被提供，而不会在数据写入电流流动时被消耗。 因此，抑制了从电源供给的负载电流的峰值。

公开(公告)号：US20050189818A1

公开(公告)日：2005-09-01

申请号：US10628384

申请日：2003-07-29

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： H03K19/00 ,  G05F1/10 ,  G11C5/06 ,  G11C5/14 ,  G11C11/407 ,  H01H47/00 ,  H02B1/24 ,  H02J1/00 ,  H02J3/00 ,  H03H11/26

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y10T307/391 ,  Y10T307/461 ,  Y10T307/696 ,  Y10T307/724 ,  Y10T307/747

摘要： Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.

摘要翻译： 电阻元件插入主电源线和主接地线，使得偏移差分放大器接收在其上产生的电压。 差分放大器控制连接到副电源线和次接地线的晶体管。 因此，从副电源线流向主接地线并从主电源线流向副接地线的漏电流规则地保持恒定。 因此，可以在保持具有分层供电结构的半导体电路装置中降低亚阈值泄漏电流的效果的同时防止在待机状态的初始阶段的操作延迟。

公开(公告)号：US20050169067A1

公开(公告)日：2005-08-04

申请号：US11099499

申请日：2005-04-06

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/15 ,  G11C5/00 ,  G11C7/00 ,  G11C7/12 ,  G11C11/00 ,  G11C11/16 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC分类号： G11C29/846 ,  G11C11/16

摘要： When normal bit lines BL3 and /BL3 are selected, spare bit lines SBL2 and /SBL2 are simultaneously selected, so that column select gates are placed in such a manner that these bit line pairs are connected to respective different read data bus pairs. The column select gates are distributed in placement so as not to cause a great difference in load capacitance between read data buses. A redundancy determination result is reflected on read data by activation of control signals φ1 and φ2 given immediately prior to a sense amplifier. Note that two sense amplifier may be provided with control signals φ1 and φ2 so as to select the outputs of one sense amplifier. With such a configuration adopted, it is possible to provide a memory device capable of performing high speed reading while realizing a redundancy replacement.

公开(公告)号：US06922355B2

公开(公告)日：2005-07-26

申请号：US10842417

申请日：2004-05-11

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C29/12 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  G11C11/00 ,  G11C5/08 ,  G11C7/00 ,  G11C7/02 ,  G11C11/34

CPC分类号： H01L27/228 ,  G11C7/14 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/224

摘要： A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

摘要翻译： 形成磁存储单元的隧道磁阻元件包括具有固定方向的固定磁场的固定磁性层，由施加的磁场磁化的自由磁性层和作为绝缘膜的隧道势垒，所述绝缘膜设置在固定和 隧道结区域中的自由磁性层。 在自由磁性层中，使用对应于具有作为存储单元的特性的容易轴区域的区域作为隧道结区域。 具有作为存储单元的不期望​​的特性的硬轴区域不被用作隧道磁阻元件的一部分。