公开(公告)号：US11532640B2

公开(公告)日：2022-12-20

申请号：US17012848

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H01L27/11597 ,  G11C11/56 ,  H01L27/11587 ,  G11C11/22 ,  H01L21/28 ,  H01L27/1159 ,  H01L29/78

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US11508755B2

公开(公告)日：2022-11-22

申请号：US17184856

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/11 ,  H01L29/51 ,  H01L29/78 ,  H01L27/1159 ,  H01L29/66 ,  H01L21/28

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

公开(公告)号：US20220367518A1

公开(公告)日：2022-11-17

申请号：US17874908

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L29/78 ,  G11C5/06 ,  G11C11/22 ,  H01L21/822 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

公开(公告)号：US20220359270A1

公开(公告)日：2022-11-10

申请号：US17814626

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/762 ,  G11C7/18 ,  H01L27/11597 ,  H01L21/8239

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

公开(公告)号：US20220285395A1

公开(公告)日：2022-09-08

申请号：US17333300

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Feng-Cheng Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

公开(公告)号：US20220285394A1

公开(公告)日：2022-09-08

申请号：US17316243

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yu Ling ,  Katherine H. Chiang ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/11587 ,  G11C11/22

Abstract: 3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.

公开(公告)号：US20220254794A1

公开(公告)日：2022-08-11

申请号：US17168361

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L23/522 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

公开(公告)号：US20210407848A1

公开(公告)日：2021-12-30

申请号：US16951595

申请日：2020-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.,

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/762 ,  H01L21/8239 ,  H01L27/11597 ,  G11C7/18

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

公开(公告)号：US11201228B2

公开(公告)日：2021-12-14

申请号：US16721335

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Chung-Te Lin ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/302 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/165

Abstract: A method includes providing a structure having a substrate, a gate structure over the substrate, a sacrificial spacer over a sidewall of the gate structure, a source/drain feature over the substrate and adjacent to the gate structure; forming a dielectric layer over the gate structure, the sacrificial spacer, and the source/drain feature; with the dielectric layer over the gate structure, the sacrificial spacer, and the source/drain feature, forming a contact extending through the dielectric layer to the source/drain feature; removing the dielectric layer to expose the sacrificial spacer; etching the sacrificial spacer to form a trench; and depositing an inter-layer dielectric (ILD) layer, wherein the ILD layer caps the trench, thereby defining an air gap inside the trench.

公开(公告)号：US20210375867A1

公开(公告)日：2021-12-02

申请号：US17116024

申请日：2020-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H Chiang ,  Chung-Te Lin

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.