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    Metal isolation testing in the context of memory cells
    123.
    发明授权
    Metal isolation testing in the context of memory cells 有权

    公开(公告)号：US11631682B2

    公开(公告)日：2023-04-18

    申请号：US16860234

    申请日：2020-04-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

    IPC: H01L27/11 ,  G06F30/398 ,  H01L23/528 ,  G11C29/50 ,  G11C29/08 ,  G11C29/04 ,  G11C29/12 ,  G06F30/39

    Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

    Three-dimensional memory device and method
    124.
    发明授权
    Three-dimensional memory device and method 有权

    公开(公告)号：US11587823B2

    公开(公告)日：2023-02-21

    申请号：US16951595

    申请日：2020-11-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

    IPC: G11C7/18 ,  H01L27/11597 ,  H01L21/8239 ,  H01L21/762

    Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

    Polysilicon resistor structures
    127.
    发明授权
    Polysilicon resistor structures 有权

    公开(公告)号：US11456293B2

    公开(公告)日：2022-09-27

    申请号：US16549077

    申请日：2019-08-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Meng-Han Lin ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair

    IPC: H01L27/06 ,  H01L21/8234

    Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

    Contacts for Semiconductor Devices and Methods of Forming the Same
    129.
    发明申请
    Contacts for Semiconductor Devices and Methods of Forming the Same 有权

    公开(公告)号：US20220115508A1

    公开(公告)日：2022-04-14

    申请号：US17146205

    申请日：2021-01-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

    IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/40

    Abstract: Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a second height greater than a height of the first contact.

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