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    Dummy Hybrid Film for Self-Alignment Contact Formation
    123.
    发明公开
    Dummy Hybrid Film for Self-Alignment Contact Formation 审中-公开

    公开(公告)号：US20230163194A1

    公开(公告)日：2023-05-25

    申请号：US17648037

    申请日：2022-01-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bor Chiuan Hsieh ,  Tsai-Jung Ho ,  Po-Cheng Shih ,  Tze-Liang Lee

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/40

    CPC classification number: H01L29/66515 ,  H01L29/401 ,  H01L29/7851 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming gate spacers on opposing sides of the dummy gate stack, forming a source/drain region on a side of the dummy gate stack, forming an inter-layer dielectric over the source/drain region, replacing the dummy gate stack with a replacement gate stack, recessing the replacement gate stack to form a recess between the gate spacers, depositing a liner extending into the recess, depositing a masking layer over the liner and extending into the recess, forming an etching mask covering a portion of the masking layer, and etching the inter-layer dielectric to form a source/drain contact opening. The source/drain region is underlying and exposed to the source/drain contact opening. A source/drain contact plug is formed in the source/drain contact opening. A gate contact plug extends between the gate spacers and electrically connecting to the replacement gate stack.

    Interconnect Structures and Methods of Forming the Same
    126.
    发明申请
    Interconnect Structures and Methods of Forming the Same 有权

    公开(公告)号：US20230135172A1

    公开(公告)日：2023-05-04

    申请号：US17710531

    申请日：2022-03-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Ren Wang ,  Jen Hung Wang ,  Tze-Liang Lee

    IPC: H01L21/768

    Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.

    Fin Field-Effect Transistor Device and Method
    129.
    发明申请
    Fin Field-Effect Transistor Device and Method 有权

    公开(公告)号：US20230025645A1

    公开(公告)日：2023-01-26

    申请号：US17592995

    申请日：2022-02-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsai-Jung Ho ,  Tze-Liang Lee

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/02

    Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a recess between gate spacers of the gate structure by recessing the gate structure below upper surfaces of the gate spacers; depositing a first layer of a dielectric material in the recess along sidewalls and a bottom of the recess; after depositing the first layer, performing a first etching process to remove portions of the first layer of the dielectric material; and after the first etching process, depositing a second layer of the dielectric material in the recess over the first layer of the dielectric material.

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