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    Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer
    121.
    发明授权
    Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer 有权
    用于通过基板晶片制造具有完全金属化通孔的封装接口基板晶片的技术

    公开(公告)号：US07880305B2

    公开(公告)日：2011-02-01

    申请号：US10290049

    申请日：2002-11-07

    申请人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

    发明人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H05K3/422 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/025 ,  H01L2924/00

    摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

    摘要翻译： 本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。 本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属 被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。 晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除 材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

    RECOVERY OF HYDROPHOBICITY OF LOW-K AND ULTRA LOW-K ORGANOSILICATE FILMS USED AS INTER METAL DIELECTRICS
    122.
    发明申请
    RECOVERY OF HYDROPHOBICITY OF LOW-K AND ULTRA LOW-K ORGANOSILICATE FILMS USED AS INTER METAL DIELECTRICS 审中-公开
    作为金属电介质的低K和超低K有机硅膜的疏水性恢复

    公开(公告)号：US20110003402A1

    公开(公告)日：2011-01-06

    申请号：US12749213

    申请日：2010-03-29

    申请人： Nirupama Chakrapani ,  Matthew E. Colburn ,  Christos D. Dimitrakopoulos ,  Dirk Pfeiffer ,  Sampath Purushothaman ,  Satyanarayana V. Nitta

    发明人： Nirupama Chakrapani ,  Matthew E. Colburn ,  Christos D. Dimitrakopoulos ,  Dirk Pfeiffer ,  Sampath Purushothaman ,  Satyanarayana V. Nitta

    IPC分类号： H01L21/30

    CPC分类号： H01L21/76826 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/31058 ,  H01L21/76807 ,  H01L21/76814 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR′Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R′ are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

    摘要翻译： 通常用于减少集成电路中的RC延迟的是多孔有机硅酸盐的介电膜，其具有二氧化硅像主链与烷基或芳基（以增加材料的疏水性并产生自由体积）直接连接到网络中的Si原子。 Si-R键在暴露于等离子体或通常用于加工的化学处理中很少存活; 这在具有开孔细孔结构的材料中尤其如此。 当Si-R键断裂时，材料由于形成亲水硅烷醇而损失疏水性，并且低介电常数受损。 使用新型甲硅烷基化剂回收材料的疏水性的方法，其可以具有通式（R2N）XSiR'Y，其中X和Y分别为1至3和3至1的整数，并且其中R和 R'选自氢，烷基，芳基，烯丙基和乙烯基部分。 由于甲硅烷基化处理，多孔有机硅酸盐的机械强度也得到改善。

    Programmable Via Devices with Air Gap Isolation
    125.
    发明申请
    Programmable Via Devices with Air Gap Isolation 有权
    具有空气间隙隔离的可编程通孔器件

    公开(公告)号：US20090305460A1

    公开(公告)日：2009-12-10

    申请号：US12544964

    申请日：2009-08-20

    申请人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

    发明人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

    IPC分类号： H01L21/06

    CPC分类号： H01L45/06 ,  H01L28/20 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

    摘要： Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; a heater over the first dielectric layer; an air gap separating at least a portion of the heater from the first dielectric layer; an isolation layer over the first dielectric layer covering at least a portion of the heater; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.

    摘要翻译： 提供可编程的器件及其制造方法。 在一个方面，提供了可编程通路装置。 可编程通孔装置包括第一介电层; 第一介电层上的加热器; 将所述加热器的至少一部分与所述第一介电层分开的气隙; 覆盖所述加热器的至少一部分的所述第一介电层上的隔离层; 在所述隔离层的与所述第一介电层相对的一侧上的覆盖层; 至少一个可编程通道，其延伸穿过所述封盖层和所述隔离层的至少一部分并与所述加热器接触，所述可编程通孔包括至少一个相变材料; 可编程通孔上的导电盖; 在覆盖层的与隔离层相对的一侧上的第二电介质层; 第一导电通孔和第二导电通孔，每个延伸穿过第二介电层，封盖层和至少一部分隔离层并与加热器接触; 以及延伸穿过所述第二介电层并与所述导电盖接触的第三导电通孔。

    INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES
    126.
    发明申请
    INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES 有权
    具有由两个光刻过程产生的三维特征的互连结构

    公开(公告)号：US20090294982A1

    公开(公告)日：2009-12-03

    申请号：US12538114

    申请日：2009-08-08

    申请人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    发明人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

    IPC分类号： H01L23/522

    CPC分类号： H01L23/53238 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level.

    摘要翻译： 一种制造互连结构的方法，用于将半导体衬底互连以具有三个不同的图案化结构，使得互连结构既提供低k和高结构完整性。 该方法包括在半导体衬底上沉积层间电介质，通过第一光刻工艺在层间电介质材料内形成第一图案，该第一光刻工艺导致在互连结构中形成通孔特征和三元特征。 该方法还包括通过第二光刻工艺在层间电介质材料内形成第二图案以在互连结构内形成线特征。 因此，该方法仅对每个互连级别仅使用两个光刻工艺形成三个独立的不同图案结构。

    Method of producing self-aligned mask in conjunction with blocking mask, articles produced by same and composition for same
    127.
    发明授权
    Method of producing self-aligned mask in conjunction with blocking mask, articles produced by same and composition for same 失效
    生产自对准面罩的方法与阻隔面罩相同，制成的物品及其成分相同

    公开(公告)号：US07517637B2

    公开(公告)日：2009-04-14

    申请号：US10804552

    申请日：2004-03-19

    申请人： Matthew E Colburn ,  Satyanarayana V Nitta ,  Sampath Purushothaman

    发明人： Matthew E Colburn ,  Satyanarayana V Nitta ,  Sampath Purushothaman

    IPC分类号： G03F7/00

    CPC分类号： G03F7/2022

    摘要： A method of forming a self aligned pattern on an existing pattern on a substrate including applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion of the masking material to preferentially develop in a fashion that replicates the existing pattern of the substrate. The existing pattern includes a first set of regions of the substrate having a first reflectivity and a second set of regions of the substrate having a second reflectivity different from the first composition. The first set of regions can include one or more metal elements and the second set of regions can include one or more dielectrics. Structures made in accordance with the method. A low resolution mask is used to block out regions over the substrate. Additionally, the resist can be applied over another masking layer that contains a separate pattern.

    摘要翻译： 一种在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩模材料的溶液的涂层，所述掩模材料为光敏或热敏感的; 进行基板的覆盖曝光; 并且允许至少一部分掩模材料以复制衬底的现有图案的方式优先显影。 现有图案包括具有第一反射率的衬底的第一组区域和具有不同于第一组成的第二反射率的衬底的第二组区域。 第一组区域可以包括一个或多个金属元素，第二组区域可以包括一个或多个电介质。 按照该方法制造的结构。 低分辨率掩模用于阻挡衬底上的区域。 另外，抗蚀剂可以施加在包含单独图案的另一掩蔽层上。

    PROGRAMMABLE VIA DEVICES WITH AIR GAP ISOLATION
    128.
    发明申请
    PROGRAMMABLE VIA DEVICES WITH AIR GAP ISOLATION 有权
    可通过具有空气隔离的装置进行编程

    公开(公告)号：US20090033360A1

    公开(公告)日：2009-02-05

    申请号：US11833354

    申请日：2007-08-03

    申请人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

    发明人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

    IPC分类号： H03K19/177 ,  H01L45/00

    CPC分类号： H01L45/06 ,  H01L28/20 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

    摘要： Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; a heater over the first dielectric layer; an air gap separating at least a portion of the heater from the first dielectric layer; an isolation layer over the first dielectric layer covering at least a portion of the heater; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.

    摘要翻译： 提供可编程的器件及其制造方法。 在一个方面，提供了可编程通路装置。 可编程通孔装置包括第一介电层; 第一介电层上的加热器; 将所述加热器的至少一部分与所述第一介电层分开的气隙; 覆盖所述加热器的至少一部分的所述第一介电层上的隔离层; 在所述隔离层的与所述第一介电层相对的一侧上的覆盖层; 至少一个可编程通道，其延伸穿过所述封盖层和所述隔离层的至少一部分并与所述加热器接触，所述可编程通孔包括至少一个相变材料; 可编程通孔上的导电盖; 在覆盖层的与隔离层相对的一侧上的第二电介质层; 第一导电通孔和第二导电通孔，每个延伸穿过第二介电层，封盖层和至少一部分隔离层并与加热器接触; 以及延伸穿过所述第二介电层并与所述导电盖接触的第三导电通孔。

    PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL
    129.
    发明申请
    PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL 有权
    通过线路后端的设备可编程

    公开(公告)号：US20090033358A1

    公开(公告)日：2009-02-05

    申请号：US11833321

    申请日：2007-08-03

    申请人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

    发明人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

    IPC分类号： H01L45/00 ,  H03K19/177

    CPC分类号： H01L28/65 ,  H01L28/20 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  Y10S977/754

    摘要： Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.

    摘要翻译： 提供可编程的器件及其制造方法。 在一个方面，提供了可编程通路装置。 可编程通孔装置包括第一介电层; 在所述第一介电层上方的至少一个隔离层; 隔离层内的加热器; 在所述隔离层的与所述第一介电层相对的一侧上的覆盖层; 至少一个可编程通道，其延伸穿过所述封盖层和所述隔离层的至少一部分并与所述加热器接触，所述可编程通孔包括至少一个相变材料; 可编程通孔上的导电盖; 在覆盖层的与隔离层相对的一侧上的第二电介质层; 第一导电通孔和第二导电通孔，每个延伸穿过第二介电层，封盖层和至少一部分隔离层并与加热器接触; 以及延伸穿过所述第二介电层并与所述导电盖接触的第三导电通孔。