公开(公告)号：US20090302454A1

公开(公告)日：2009-12-10

申请号：US12462980

申请日：2009-08-11

申请人： Yu- Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

发明人： Yu- Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H05K3/422 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/025 ,  H01L2924/00

摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

摘要翻译： 本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。 本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属 被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。 晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除 材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

公开(公告)号：US07880305B2

公开(公告)日：2011-02-01

申请号：US10290049

申请日：2002-11-07

申请人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

发明人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/422 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/025 ,  H01L2924/00

摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

摘要翻译： 本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。 本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属 被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。 晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除 材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

公开(公告)号：US06732908B2

公开(公告)日：2004-05-11

申请号：US10052591

申请日：2002-01-18

申请人： Bruce Kenneth Furman ,  Maheswaran Surendra ,  Sherif A. Goma ,  Simon M. Karecki ,  John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

发明人： Bruce Kenneth Furman ,  Maheswaran Surendra ,  Sherif A. Goma ,  Simon M. Karecki ,  John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： B23K3102

CPC分类号： H01L24/12 ,  H01L21/288 ,  H01L21/2885 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13582 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2224/45111 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.

摘要翻译： 一个微型接头互连结构，包括具有精确可控高度的密集阵列的金属螺柱，并具有接合冶金。 该阵列在要连接到载体的装置芯片上或与其他装置一起在载体上产生，其中一些装置芯片可被选择为具有相似的互连结构，以便将组装的载体形成为一体， 完整的计算，通信或网络系统。

公开(公告)号：US07276787B2

公开(公告)日：2007-10-02

申请号：US10729254

申请日：2003-12-05

申请人： Daniel Charles Edelstein ,  Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Jon Alfred Casey ,  Sherif A. Goma ,  Raymond R. Horton ,  Gareth Geoffrey Hougham ,  Michael Wayne Lane ,  Xiao Hu Liu ,  Chirag Suryakant Patel ,  Edmund Juris Sprogis ,  Michelle Leigh Steen ,  Brian Richard Sundlof ,  Cornelia K. Tsang ,  George Frederick Walker

发明人： Daniel Charles Edelstein ,  Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Jon Alfred Casey ,  Sherif A. Goma ,  Raymond R. Horton ,  Gareth Geoffrey Hougham ,  Michael Wayne Lane ,  Xiao Hu Liu ,  Chirag Suryakant Patel ,  Edmund Juris Sprogis ,  Michelle Leigh Steen ,  Brian Richard Sundlof ,  Cornelia K. Tsang ,  George Frederick Walker

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/4763 ,  H01L29/40 ,  H01L23/52

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US07688095B2

公开(公告)日：2010-03-30

申请号：US11741345

申请日：2007-04-27

申请人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

发明人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

IPC分类号： G01R31/02

CPC分类号： G01R1/0735 ,  G01R3/00 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4038

摘要： Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 μm.

摘要翻译： 描述了用于半导体工业的柔性和刚性插入件及其制造方法。 自动催化过程用于最小化与柔性插入物的生产相关的成本，同时提高产量和寿命。 电接触区域容易隔离，并且由于插入器的所有部分一次镀覆，因此腐蚀的风险降低。 从插入件的柔性部分突出的引线可容纳更多种待测试的部件。 刚性插入件包括从固定到基板的探针垫突出的销。 针的刚度穿过待测接触垫上的氧化物。 易于使用的半导体材料和工艺用于制造根据本发明的柔性和刚性插入件。 柔性和刚性插入件可以容纳低至25μm的间距。

公开(公告)号：US20100038126A1

公开(公告)日：2010-02-18

申请号：US12542935

申请日：2009-08-18

申请人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

发明人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

IPC分类号： H05K1/11

CPC分类号： G01R1/0735 ,  G01R3/00 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4038

摘要： Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 μm.

摘要翻译： 描述了用于半导体工业的柔性和刚性插入件及其制造方法。 自动催化过程用于最小化与柔性插入物的生产相关的成本，同时提高产量和寿命。 电接触区域容易隔离，并且由于插入器的所有部分一次镀覆，因此腐蚀的风险降低。 从插入件的柔性部分突出的引线可容纳更多种待测试的部件。 刚性插入件包括从固定到基板的探针垫突出的销。 针的刚度穿过待测接触垫上的氧化物。 易于使用的半导体材料和工艺用于制造根据本发明的柔性和刚性插入件。 柔性和刚性插入件可以容纳低至25μm的间距。

公开(公告)号：US07452212B2

公开(公告)日：2008-11-18

申请号：US11718279

申请日：2005-09-30

申请人： Gareth Geoffrey Hougham ,  Ali Afzali ,  Steven Allen Cordes ,  Paul W. Coteus ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Alphonso P. Lanzetta ,  Daniel Peter Morris ,  Joanna Rosner ,  Nisha Yohannan

发明人： Gareth Geoffrey Hougham ,  Ali Afzali ,  Steven Allen Cordes ,  Paul W. Coteus ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Alphonso P. Lanzetta ,  Daniel Peter Morris ,  Joanna Rosner ,  Nisha Yohannan

IPC分类号： H01R9/00

CPC分类号： H01R9/00 ,  B33Y80/00 ,  G01R1/06738 ,  G01R1/07314 ,  G01R3/00 ,  H01R13/2414 ,  H05K7/1061 ,  Y10T29/49002

摘要： Techniques for forming enhanced electrical connections are provided. In one aspect, an electrical connecting device comprises an electrically insulating carrier having one or more contact structures traversing a plane thereof. Each contact structure comprises an elastomeric material having an electrically conductive layer running along at least one surface thereof continuously through the plane of the carrier.

摘要翻译： 提供了用于形成增强的电连接的技术。 一方面，电连接装置包括具有穿过其平面的一个或多个接触结构的电绝缘载体。 每个接触结构包括具有连续穿过载体平面的至少一个表面延伸的导电层的弹性体材料。

公开(公告)号：US08187923B2

公开(公告)日：2012-05-29

申请号：US12167745

申请日：2008-07-03

申请人： Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

发明人： Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/67092 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  Y10S414/139 ,  H01L2924/00 ,  H01L2224/0401

摘要： A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

摘要翻译： 提供了用于避免载波边缘破裂的集成电路模块的激光释放和玻璃切屑去除工艺。

公开(公告)号：US08159248B2

公开(公告)日：2012-04-17

申请号：US12542935

申请日：2009-08-18

申请人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

发明人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

IPC分类号： G01R31/00

CPC分类号： G01R1/0735 ,  G01R3/00 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4038

摘要： Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 μm.

摘要翻译： 描述了用于半导体工业的柔性和刚性插入件及其制造方法。 自动催化过程用于最小化与柔性插入物的生产相关的成本，同时提高产量和寿命。 电接触区域容易隔离，并且由于插入器的所有部分一次镀覆，因此腐蚀的风险降低。 从插入件的柔性部分突出的引线可容纳更多种待测试的部件。 刚性插入件包括从固定到基板的探针垫突出的销。 针的刚度穿过待测接触垫上的氧化物。 易于使用的半导体材料和工艺用于制造根据本发明的柔性和刚性插入件。 柔性和刚性插入件可以容纳低至25μm的间距。

公开(公告)号：US20110130005A1

公开(公告)日：2011-06-02

申请号：US13024711

申请日：2011-02-10

申请人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

发明人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

IPC分类号： H01L21/3105

CPC分类号： H01L21/31051 ,  B81C1/00611 ,  B81C2201/0119 ,  H01L21/0272 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76838

摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。