公开(公告)号：US20210296570A1

公开(公告)日：2021-09-23

申请号：US17338632

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

公开(公告)号：US20210257542A1

公开(公告)日：2021-08-19

申请号：US17308057

申请日：2021-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L29/82 ,  G11C11/16 ,  H01L43/08 ,  G11C5/06

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.

公开(公告)号：US11063206B2

公开(公告)日：2021-07-13

申请号：US16438480

申请日：2019-06-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L29/82 ,  G11C11/16 ,  H01L43/08 ,  G11C5/06 ,  H01L27/22

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.

公开(公告)号：US10991873B2

公开(公告)日：2021-04-27

申请号：US16166173

申请日：2018-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  H01L23/528 ,  H01L21/768 ,  H01L27/22 ,  H01L23/522 ,  H01L43/10

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a liner on the MTJ; removing part of the liner to form a recess exposing the MTJ; and forming a conductive layer in the recess, wherein top surfaces of the conductive layer and the liner are coplanar. Preferably the MTJ further includes: a bottom electrode on the substrate, a fixed layer on the bottom electrode, and a top electrode on the fixed layer, in which the conductive layer and the top electrode are made of same material.

公开(公告)号：US10910553B1

公开(公告)日：2021-02-02

申请号：US16531129

申请日：2019-08-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jun Xie

IPC: H01L43/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US20210020691A1

公开(公告)日：2021-01-21

申请号：US16532492

申请日：2019-08-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Ying-Cheng Liu ,  Yi-Hui Lee ,  Chin-Yang Hsieh ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16

Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.

公开(公告)号：US20200144490A1

公开(公告)日：2020-05-07

申请号：US16208566

申请日：2018-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Chin-Yang Hsieh

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The semiconductor device includes the substrate, the connection structure, the first IMD layer, the MTJ structure, and the second IMD layer. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

公开(公告)号：US20200083428A1

公开(公告)日：2020-03-12

申请号：US16166173

申请日：2018-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  H01L23/528 ,  H01L21/768 ,  H01L27/22 ,  H01L23/522

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a liner on the MTJ; removing part of the liner to form a recess exposing the MTJ; and forming a conductive layer in the recess, wherein top surfaces of the conductive layer and the liner are coplanar. Preferably the MTJ further includes: a bottom electrode on the substrate, a fixed layer on the bottom electrode, and a top electrode on the fixed layer, in which the conductive layer and the top electrode are made of same material.

公开(公告)号：US09673053B2

公开(公告)日：2017-06-06

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

公开(公告)号：US20160172496A1

公开(公告)日：2016-06-16

申请号：US14599556

申请日：2015-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Chun-Hsien Lin ,  Chen-Yi Weng

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a pair of recess regions disposed on two sides of the bottom of the metal gate.

Abstract translation: 具有外延结构的场效应晶体管包括鳍状结构和横跨鳍状结构的金属栅极。 金属栅极包括设置在金属栅极底部两侧的一对凹陷区域。