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公开(公告)号：US07120895B2
公开(公告)日：2006-10-10
申请号：US11084484
申请日：2005-03-18
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US20060221646A1
公开(公告)日：2006-10-05
申请号：US11102611
申请日：2005-04-07
申请人： Jun Ye , Zhen Zhu , Shifeng Zhao , Lieyi Fang , Zhiliang Chen
发明人： Jun Ye , Zhen Zhu , Shifeng Zhao , Lieyi Fang , Zhiliang Chen
IPC分类号： H02M7/00
摘要： System and method for providing frequency control to a power converter. The system includes a pseudorandom signal generator configured to generate a digital signal. The digital signal is associated with at least an N-bit datum, and N is a positive integer. Additionally, the system includes a digital-to-analog converter configured to receive the digital signal and generate a first control signal, an output signal generator configured to receive the first control signal and generate at least a first output signal associated with a frequency, and a pulse-width-modulation generator configured to receive at least the first output signal. The N-bit datum represents a pseudorandom number.
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公开(公告)号：US07117477B2
公开(公告)日：2006-10-03
申请号：US11024121
申请日：2004-12-28
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US07114145B2
公开(公告)日：2006-09-26
申请号：US10989972
申请日：2004-11-16
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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125.发明授权Adaptive multi-level threshold system and method for power converter protection 有权自适应多电平阈值系统和电源转换器保护方法公开(公告)号：US07099164B2
公开(公告)日：2006-08-29
申请号：US11051242
申请日：2005-02-04
申请人： Zhen Zhu , Jun Ye , Shifeng Zhao , Lieyi Fang , Zhiliang Chen
发明人： Zhen Zhu , Jun Ye , Shifeng Zhao , Lieyi Fang , Zhiliang Chen
CPC分类号： H02M1/32 , H02M3/33507
摘要： System and method for protecting a power converter. The system includes a compensation system configured to receive an input signal and generate a control signal, a cycle threshold generator configured to receive the control signal and generate a cycle threshold, and a comparator configured to receive the cycle threshold and a feedback signal and generate a comparison signal. Additionally, the system includes a pulse-width-modulation generator configured to receive the comparison signal and generate a modulation signal in response to the comparison signal, and a switch configured to receive the modulation signal and control an input current for a power converter. The input current is associated with an output power for the power converter. The cycle threshold corresponds to a threshold power level for the output power. The threshold power level is constant, decreases, or increases with respect to the input signal.
摘要翻译： 保护电源转换器的系统和方法。 该系统包括被配置为接收输入信号并产生控制信号的补偿系统，配置成接收控制信号并产生周期阈值的周期阈值发生器，以及配置成接收周期阈值和反馈信号并产生 比较信号。 此外，该系统包括：脉冲宽度调制发生器，被配置为接收比较信号并响应于比较信号产生调制信号;以及开关，被配置为接收调制信号并控制功率转换器的输入电流。 输入电流与功率转换器的输出功率有关。 周期阈值对应于输出功率的阈值功率电平。 阈值功率电平相对于输入信号是恒定的，减小的或增加的。
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公开(公告)号：US07027635B1
公开(公告)日：2006-04-11
申请号：US10193965
申请日：2002-07-10
申请人： Mark J. Wihl , George Q. Chen , Jun Ye , Lih-Huah Yiin , Pei-Chun Chiang
发明人： Mark J. Wihl , George Q. Chen , Jun Ye , Lih-Huah Yiin , Pei-Chun Chiang
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G03F1/30 , G03F1/50 , G03F1/84 , G06T2207/30148
摘要： Techniques that use the design databases used in each of the expose/etch steps during construction of phase shift masks are described. A model or reference image is rendered, accounting for systematic variations, from the design databases to represent what a layer of the PSM should look like after processing. The reference image is compared to an optically acquired image of a specimen phase shift mask to find defects. The technique of the present invention can be used to inspect EAPSM, APSM and tritone masks. The technique inspects all layers in one pass and is therefore more efficient.
摘要翻译： 描述了在构造相移掩模期间使用在每个曝光/蚀刻步骤中使用的设计数据库的技术。 渲染来自设计数据库的模型或参考图像，以计算系统的变化，以表示处理后的PSM层的外观。 将参考图像与样本相移掩模的光学获取图像进行比较以发现缺陷。 本发明的技术可用于检查EAPSM，APSM和三色面罩。 该技术在一次通过中检查所有层，因此效率更高。
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公开(公告)号：US06969837B2
公开(公告)日：2005-11-29
申请号：US10863915
申请日：2004-06-09
申请人： Jun Ye , R. Fabian W. Pease , Xun Chen
发明人： Jun Ye , R. Fabian W. Pease , Xun Chen
IPC分类号： G01N21/956 , G01J1/02 , G01J1/04 , G01M11/00 , G03F1/08 , G03F7/20 , H01L21/027 , H01L27/14 , H01L27/00
CPC分类号： G03F7/7085 , G03F7/70591 , G03F7/7065
摘要： A system and sensor for measuring, inspecting, characterizing, evaluating and/or controlling optical lithographic equipment and/or materials used therewith, for example, photomasks. In one embodiment, the system and sensor measures, collects and/or detects an aerial image (or portion thereof) produced or generated by the interaction between the photomask and lithographic equipment. An image sensor unit may measure, collect, sense and/or detect the aerial image in situ—that is, the aerial image at the wafer plane produced, in part, by a production-type photomask (i.e., a wafer having integrated circuits formed therein/thereon) and/or by associated lithographic equipment used, or to be used, to manufacture of integrated circuits. A processing unit, coupled to the image sensor unit, may generate image data which is representative of the aerial image by interleaving the intensity of light sampled by each sensor cell at the plurality of location of the platform.
摘要翻译： 用于测量，检查，表征，评估和/或控制与其一起使用的光学平版印刷设备和/或材料的系统和传感器，例如光掩模。 在一个实施例中，系统和传感器测量，收集和/或检测由光掩模和光刻设备之间的相互作用产生或产生的空间图像（或其部分）。 图像传感器单元可以原位测量，收集，感测和/或检测空中图像，即在晶片平面上的部分由生产型光掩模（即，形成有集成电路的晶片）产生的空间图像 其中/之上）和/或通过使用或用于制造集成电路的相关平版印刷设备。 耦合到图像传感器单元的处理单元可以通过交织由平台的多个位置处的每个传感器单元采样的光的强度来生成代表空间图像的图像数据。
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公开(公告)号：US20050166174A1
公开(公告)日：2005-07-28
申请号：US11084484
申请日：2005-03-18
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US20050125184A1
公开(公告)日：2005-06-09
申请号：US11041807
申请日：2005-01-24
CPC分类号： H01L21/67276 , G01D9/005 , H01L21/67253 , H01L22/34 , H01L2224/48463 , H01L2224/49107 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： In one aspect, the present invention is a sensor unit for sensing process parameters of a process to manufacture an integrated circuit using integrated circuit processing equipment. In one embodiment, the sensor unit includes a substrate having a wafer-shaped profile and a first sensor, disposed on or in the substrate, to sample a first process parameter. The sensor unit of this embodiment also includes a second sensor, disposed on or in the substrate, to sample a second process parameter wherein the second process parameter is different from the first process parameter. In one embodiment, the sensor unit includes a first source, disposed on or in the substrate, wherein first source generates an interrogation signal and wherein the first sensor uses the interrogation signal from the first source to sample the first process parameter. The sensor unit may also include a second source, disposed on or in the substrate, wherein second source generates an interrogation signal and wherein the second sensor uses the interrogation signal from the second source to sample the second process parameter. The first sensor and the first source may operate in an end-point mode or in a real-time mode. In this regard, the first sensor samples the first parameter periodically or continuously while the sensor unit is disposed in the integrated circuit processing equipment and undergoing processing. In one embodiment, the first sensor is a temperature sensor and the second sensor is a pressure sensor, a chemical sensor, a surface tension sensor or a surface stress sensor.
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公开(公告)号：US06828542B2
公开(公告)日：2004-12-07
申请号：US10390806
申请日：2003-03-18
申请人： Jun Ye , R. Fabian W. Pease , Xun Chen
发明人： Jun Ye , R. Fabian W. Pease , Xun Chen
IPC分类号： H01L2700
CPC分类号： G03F7/7085 , G03F7/70591 , G03F7/7065
摘要： In one aspect, the present invention is a technique of, and a system and sensor for measuring, inspecting, characterizing and/or evaluating optical lithographic equipment, methods, and/or materials used therewith, for example, photomasks. In one embodiment of this aspect of the invention, the system, sensor and/or technique measures, collects and/or detects an aerial image produced or generated by the interaction between the photomask and lithographic equipment. An image sensor unit may measure, collect, sense and/or detect the aerial image in situ—that is, the aerial image at the wafer plane produced, in part, by a production-type photomask (i.e., a wafer having integrated circuits formed during the integrated circuit fabrication process) and/or by associated lithographic equipment used, or to be used, to manufacture of integrated circuits.
摘要翻译： 一方面，本发明是用于测量，检查，表征和/或评估与其一起使用的光学平版印刷设备，方法和/或材料的技术，以及系统和传感器，例如光掩模。 在本发明的该方面的一个实施例中，系统，传感器和/或技术测量，收集和/或检测由光掩模和光刻设备之间的相互作用产生或产生的空间图像。 图像传感器单元可以原位测量，收集，感测和/或检测空中图像，即，晶片平面上的空间图像，部分地由生产型光掩模（即，已形成集成电路的晶片 在集成电路制造工艺期间）和/或通过使用或被使用的相关光刻设备来制造集成电路。
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