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公开(公告)号：US11495321B2
公开(公告)日：2022-11-08
申请号：US17387335
申请日：2021-07-28
IPC分类号： G11C29/42 , G11C29/44 , G11C5/02 , G11C11/4074 , G11C11/4091 , G11C29/02
摘要： Methods, systems, and devices for method for setting a reference voltage for read operations are described. A memory device may perform a first read operation on a set of memory cells using a first reference voltage and detect a first codeword based on performing the first read operation using the first reference voltage. The memory device may compare a first quantity of bits of the first codeword having a first logic value (e.g., a logic value ‘1’) with an expected quantity of bits having the first logic value (e.g., the expected quantity of logic value ‘1’s stored by the set of memory cells). The memory device may determine whether to perform a second read operation on the set of memory cells using a second reference voltage different than the first reference voltage (e.g., greater or less than the first reference voltage) based on the comparing.
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公开(公告)号：US11495320B2
公开(公告)日：2022-11-08
申请号：US17169643
申请日：2021-02-08
发明人： Heejong Kim , Gunbae Kim
摘要： A storage device includes a power supply circuit that receives a power disable signal from a host device and provides a first internal voltage and a second internal voltage, a non-volatile memory including a memory device, and a storage controller that controls the non-volatile memory and includes a processor that performs a data recovery operation on data stored in the memory device and a host interface that communicates with the host device. When the power disable signal is activated at a power off time, the storage controller is powered off, the power supply circuit interrupts the first internal voltage and the second internal voltage during a reference time following the power off time, and provides the first internal voltage to the processor after the reference time has elapsed following the power off time.
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公开(公告)号：US11495319B2
公开(公告)日：2022-11-08
申请号：US17162544
申请日：2021-01-29
申请人： SK hynix Inc.
发明人： Jeen Park
摘要： Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to embodiments of the present disclosure, a memory system may perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage. Accordingly, the memory system is capable of minimizing the time of operation in the state in which a bit-flip occurs and preventing a problem in which irrecoverable data is recorded in a memory device due to malfunction of firmware.
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124.发明授权公开(公告)号：US11495279B1
公开(公告)日：2022-11-08
申请号：US17402984
申请日：2021-08-16
IPC分类号： G11C11/406 , G11C29/42 , G11C11/4096
摘要： A write operation performed on a first memory unit of a memory device is detected, wherein the first memory unit comprises one or more memory cells. Responsive to detecting the write operation, a value of a counter associated with the first memory unit is incremented. It is determined whether the value of the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a defined range. Responsive to determining that the value of the counter satisfies the threshold criterion, a refresh operation is performed on a second memory unit.
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公开(公告)号：US20220351800A1
公开(公告)日：2022-11-03
申请号：US17813079
申请日：2022-07-18
摘要： Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.
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126.发明申请公开(公告)号：US20220351758A1
公开(公告)日：2022-11-03
申请号：US17748866
申请日：2022-05-19
摘要： The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.
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公开(公告)号：US11488682B2
公开(公告)日：2022-11-01
申请号：US16911333
申请日：2020-06-24
发明人： Tomer Eliash , Alexander Bazarsky , Eran Sharon
摘要： An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.
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128.发明授权公开(公告)号：US11487610B2
公开(公告)日：2022-11-01
申请号：US15975703
申请日：2018-05-09
摘要： Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.
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公开(公告)号：US20220336036A1
公开(公告)日：2022-10-20
申请号：US17502590
申请日：2021-10-15
申请人： SK hynix Inc.
发明人： Jong Ha LEE , Min Hwan MOON
摘要： A storage device includes a memory device and a memory controller. The memory device stores a history read table including root bit information, read voltage information, and error bit information on each of a plurality of memory blocks, and performs a read operation of reading data stored in the plurality of memory blocks based on the history read table. When the read operation fails, a memory controller changes a level of a read voltage, and controls the memory device to perform a read retry operation of retrying the read operation by using the changed read voltage. When the read retry operation passes, the memory controller determines whether the history read table is to be updated by comparing the root bit information of the read retry operation with the root bit information of the history read table.
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公开(公告)号：US20220328121A1
公开(公告)日：2022-10-13
申请号：US17737781
申请日：2022-05-05
发明人： Yingquan Wu
摘要： A level count disparity is determined based at least in part on: (1) an expected count of a plurality of cells in solid state storage and (2) an observed count of the plurality of cells in the solid state storage, where the observed count is associated with a number of cells in the solid state storage that are activated by performing a single read on the solid state storage using a previous read threshold. A next read threshold is determined, including by: determining a direction relative to the previous read threshold based at least in part on the level count disparity and independent of the second and earlier level count disparity; and determining a magnitude based at least in part on the level count disparity and the second and earlier level count disparity. Read data is obtained using the next read threshold and error correction decoding is performed.
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