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公开(公告)号：US20220223214A1
公开(公告)日：2022-07-14
申请号：US17149136
申请日：2021-01-14
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Huai-yuan Tseng , Tomer Eliash
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus also includes a control circuit coupled to the word lines and the bit lines and configured to determine whether a program operation of the memory cells involves all of the plurality of planes. In response to the program operation of the memory cells not involving all of the plurality of planes, the control circuit adjusts at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation based on a quantity of the plurality of planes associated with the memory cells being program-verified in the program operation.
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公开(公告)号：US11037635B1
公开(公告)日：2021-06-15
申请号：US16784171
申请日：2020-02-06
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Tomer Eliash , Huai-Yuan Tseng
Abstract: Apparatuses and techniques are described for managing power consumption in a memory device. When a multi-plane read command is received, a control circuit determines whether the blocks identified by the read command are fully or partially programmed. If they are fully programmed, the read command is executed while applying a common read pass voltage to the unprogrammed word lines of the respective blocks. If the blocks are not all fully programmed, the control circuit determines a last-programmed word line. If the last-programmed word lines are not equal in each block, the read command is executed while applying a base read pass voltage to the unprogrammed word lines of one or more higher-programmed blocks and a lower read pass voltage to the unprogrammed word lines of one or more lower-programmed blocks.
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公开(公告)号：US20230069260A1
公开(公告)日：2023-03-02
申请号：US17461922
申请日：2021-08-30
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Jiahui Yuan , Tomer Eliash
Abstract: Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.
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公开(公告)号：US20220383961A1
公开(公告)日：2022-12-01
申请号：US17329390
申请日：2021-05-25
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Tomer Eliash , Huai-Yuan Tseng
Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.
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公开(公告)号：US11488682B2
公开(公告)日：2022-11-01
申请号：US16911333
申请日：2020-06-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Tomer Eliash , Alexander Bazarsky , Eran Sharon
Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11226772B1
公开(公告)日：2022-01-18
申请号：US16912381
申请日：2020-06-25
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Mark Murin , Hua-Ling Cynthia Hsu , Tomer Eliash , Huai-Yuan Tseng , Deepanshu Dutta
IPC: G06F3/06 , G11C16/10 , G11C16/32 , H01L25/065 , G11C16/04
Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.
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公开(公告)号：US20210407613A1
公开(公告)日：2021-12-30
申请号：US16911333
申请日：2020-06-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Tomer Eliash , Alexander Bazarsky , Eran Sharon
Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.
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公开(公告)号：US11664075B2
公开(公告)日：2023-05-30
申请号：US17461922
申请日：2021-08-30
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Jiahui Yuan , Tomer Eliash
CPC classification number: G11C16/102 , G11C16/0433 , G11C16/08 , G11C16/16 , G11C16/26
Abstract: Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.
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公开(公告)号：US20220284965A1
公开(公告)日：2022-09-08
申请号：US17192598
申请日：2021-03-04
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Huai-yuan Tseng , Swaroop Kaza , Tomer Eliash
Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.
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10.发明申请公开(公告)号：US20210405920A1
公开(公告)日：2021-12-30
申请号：US16912381
申请日：2020-06-25
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Mark Murin , Hua-Ling Cynthia Hsu , Tomer Eliash , Huai-Yuan Tseng , Deepanshu Dutta
IPC: G06F3/06 , G11C16/10 , G11C16/32 , H01L25/065
Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.
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