公开(公告)号：US07391636B2

公开(公告)日：2008-06-24

申请号：US11863151

申请日：2007-09-27

Applicant: Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

Inventor： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

IPC: G11C5/06

CPC classification number: H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and an arrangement method thereof are included. The semiconductor memory device includes column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract translation: 包括半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。

公开(公告)号：US07296110B2

公开(公告)日：2007-11-13

申请号：US11071586

申请日：2005-03-04

Applicant: Hoe-ju Chung ,  Jung-bae Lee

Inventor： Hoe-ju Chung ,  Jung-bae Lee

IPC: G06F12/00

CPC classification number: G06F13/4243

Abstract: Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

Abstract translation: 提供了一种可以高速初始化数据信道的存储器系统和方法，而不需要增加半导体存储器件中的引脚数量，并且不需要电路来执行初始化。 存储器系统包括配备有多个半导体存储器件的存储器模块; 控制半导体存储器件的存储器控​​制器; 以及连接在所述多个半导体存储器件和所述存储器控制器之间的数据通道和命令/地址通道，其中所述多个半导体存储器件的读取延迟和写入延迟由所述存储器控制器控制。

公开(公告)号：US07269043B2

公开(公告)日：2007-09-11

申请号：US11082551

申请日：2005-03-17

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: G11C5/06

CPC classification number: G11C5/04 ,  G11C29/028 ,  G11C29/38 ,  G11C29/50008 ,  G11C2207/2254

Abstract: Disclosed is a memory module and a method of calibrating an impedance of a semiconductor memory device of the memory module, where the memory module includes semiconductor memory devices each having a separate terminal for calibrating impedance characteristics, and a reference resistor commonly connected to the separate terminals, such that the number of reference resistors used in calibration of impedance characteristics of an off-chip driver or an on-die termination circuit of the semiconductor memory device is reduced.

Abstract translation: 公开了一种校准存储器模块的半导体存储器件的阻抗的存储器模块和方法，其中存储器模块包括各自具有用于校准阻抗特性的单独端子的半导体存储器件，以及通常连接到单独端子的参考电阻器 使得用于校准半导体存储器件的片外驱动器或片上终端电路的阻抗特性的参考电阻器的数量减少。

公开(公告)号：US20060109382A1

公开(公告)日：2006-05-25

申请号：US11273406

申请日：2005-11-15

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: H04N9/74

CPC classification number: H04N5/44504 ,  H04N21/426

Abstract: A display apparatus and control method thereof. The display apparatus includes a first processor outputting a on-screen display (OSD) video signal or a processed first video signal including an OSD window; an OSD extractor extracting the OSD window from the OSD video signal; and a second processor mixing an externally inputted second video signal and the OSD window extracted from the OSD extractor, and outputting the mixed signal. A display apparatus is thus provided which generates a uniform OSD window and reduces costs.

Abstract translation: 一种显示装置及其控制方法。 该显示装置包括输出屏幕显示（OSD）视频信号的第一处理器或包括OSD窗口的经处理的第一视频信号; OSD提取器，从OSD视频信号中提取OSD窗口; 以及混合从外部输入的第二视频信号和从OSD提取器提取的OSD窗口的第二处理器，并输出混合信号。 因此提供了一种产生统一的OSD窗口并降低成本的显示装置。

公开(公告)号：US07016237B2

公开(公告)日：2006-03-21

申请号：US10771488

申请日：2004-02-04

Applicant: Jung-bae Lee ,  One-gyun La

Inventor： Jung-bae Lee ,  One-gyun La

IPC: G11C7/00

CPC classification number: G11C7/1093 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

公开(公告)号：US20060056218A1

公开(公告)日：2006-03-16

申请号：US11221684

申请日：2005-09-08

Applicant: Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

Inventor： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

Abstract translation: 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿着与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

公开(公告)号：US20060055045A1

公开(公告)日：2006-03-16

申请号：US11225221

申请日：2005-09-12

Applicant: Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

Inventor： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

IPC: H01L29/40

CPC classification number: H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract translation: 公开了一种半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。

公开(公告)号：US20050243627A1

公开(公告)日：2005-11-03

申请号：US11105169

申请日：2005-04-12

Applicant: Yun-Sang Lee ,  Jung-Bae Lee

Inventor： Yun-Sang Lee ,  Jung-Bae Lee

IPC: G11C11/401 ,  G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40611 ,  G11C11/406 ,  G11C11/40618

Abstract: Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

Abstract translation: 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 当所有存储体地址已被提供给当前行时，SDRAM电路更新当前刷新行并重复该过程。 该过程可以允许存储器控制器根据需要修改自动刷新存储体序列，使得自动刷新操作可以在一些存储体上与对其它存储体的读取和写入同时进行，从而更好地利用SDRAM电路。 描述和要求保护其他实施例。

公开(公告)号：US20050190634A1

公开(公告)日：2005-09-01

申请号：US10974951

申请日：2004-10-28

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G06F13/14 ,  G06F11/10 ,  G06F13/16 ,  G11C7/10 ,  G11C8/00 ,  G11C8/06

CPC classification number: G11C7/10 ,  G06F11/1044 ,  G06F13/1668 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/06

Abstract: A memory system using a simultaneous bidirectional input/output (SBD I/O) circuit on an address bus line. The memory system includes a first address I/O circuit and a second address I/O circuit, which are connected by the address bus line. The first address I/O circuit may be included in a controller, transmits an address signal to the address bus line, and receives an acknowledgement signal from the address bus line. The second address I/O circuit may be included in a memory device (such as dynamic random access memory (DRAM)), transmits the acknowledgement signal to the address bus line, and receives the address signal from the address bus line. The memory system may also include an error correction circuit unit which generates the acknowledgement signal indicating if an error is present in the address signal received by the second address I/O circuit.

Abstract translation: 在地址总线上使用同时双向输入/输出（SBD I / O）电路的存储器系统。 存储器系统包括通过地址总线连接的第一地址I / O电路和第二地址I / O电路。 第一地址I / O电路可以包括在控制器中，将地址信号发送到地址总线，并从地址总线接收确认信号。 第二地址I / O电路可以包括在存储器件（例如动态随机存取存储器（DRAM））中，将确认信号发送到地址总线，并从地址总线接收地址信号。 存储器系统还可以包括纠错电路单元，其产生指示在由第二地址I / O电路接收的地址信号中是否存在错误的确认信号。

公开(公告)号：US20050116746A1

公开(公告)日：2005-06-02

申请号：US10990412

申请日：2004-11-18

Applicant: Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

Inventor： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

IPC: H03K19/0175 ,  H03K19/003 ,  H03B1/00

CPC classification number: H03K19/003

Abstract: An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

Abstract translation: 输入缓冲器，用于检测输入信号。 输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截 当参考电压信号的电压电平等于预定电压电平时，控制信号。