DYNAMIC CURRENT SCALING OF A REGULATOR
    132.
    发明公开

    公开(公告)号:US20230367342A1

    公开(公告)日:2023-11-16

    申请号:US17741994

    申请日:2022-05-11

    CPC classification number: G05F1/10

    Abstract: A method and apparatus for performing dynamic current scaling of an input current of a voltage regulator are provided. The method and apparatus allow tuning current consumption in various applications, calculating a duration of an activity phase in which various algorithms are executed and activating dynamic current scaling of a regulator if the activity duration is shorter than a programmable threshold. A controller receives a threshold for an activity duration and a window size in which to evaluate the activity duration.

    CIRCUIT HAVING AN AMPLIFIER STAGE AND A CURRENT MIRROR LOOP OR STABILITY NETWORK

    公开(公告)号:US20230361737A1

    公开(公告)日:2023-11-09

    申请号:US18303931

    申请日:2023-04-20

    CPC classification number: H03F3/45475 H03F3/45273 H03F1/483 H03F1/086

    Abstract: A circuit an amplifier stage that amplifier stage includes a positive amplifier branch and a negative amplifier branch and has current flow paths therethrough cascaded in a flow line for a core current for the amplifier stage between a supply node and a ground node. The positive and negative amplifier branches have respective input nodes configured to receive an input signal applied therebetween. A current mirror loop can be coupled to the respective input nodes of the positive and negative amplifier branches and provides an adjustable high-impedance bias source for the core current for the amplifier stage. In addition to, or instead of the current mirror loop, the circuit can include stability network having a gain bandwidth range. The amplifier stage is configured to short-circuit the output signal from the amplifier stage within the gain bandwidth range based on an output voltage setting signal.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

    公开(公告)号:US20230361010A1

    公开(公告)日:2023-11-09

    申请号:US18140194

    申请日:2023-04-27

    Inventor: Riccardo VILLA

    Abstract: A semiconductor chip or die is arranged on a first surface of a thermally conductive die pad of a substrate such as a leadframe. An encapsulation of insulating material in molded onto the die pad having the semiconductor die arranged on the first surface. At the second surface of the die pad, opposite the first surface, the encapsulation borders on the die pad at a borderline around the die pad. A recessed portion of the encapsulation is provided, for example, via laser ablation, at the borderline around the die pad. Thermally conductive material such as metal material is filled in the recessed portion of the encapsulation around the die pad. The surface area of the thermally conductive die pad is augmented by the filling of thermally conductive material in the recessed portion of the encapsulation thus improving thermal performance of the device.

    Semiconductor package with die stacked on surface mounted devices

    公开(公告)号:US11810839B2

    公开(公告)日:2023-11-07

    申请号:US17674697

    申请日:2022-02-17

    Inventor: Cristina Somma

    Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.

    CONTROL MODULE FOR A RESONANT SWITCHED-CAPACITOR CONVERTER AND METHOD FOR CONTROLLING A RESONANT SWITCHED-CAPACITOR CONVERTER

    公开(公告)号:US20230353052A1

    公开(公告)日:2023-11-02

    申请号:US18300945

    申请日:2023-04-14

    CPC classification number: H02M3/158 H02M1/0009 H02M1/083

    Abstract: A control module, for a resonant switched-capacitor converter with an inductor, includes a controller stage, an input stage generating a control signal indicating a control quantity, a delay stage generating a duration signal indicating a time quantity, and a circuit indicating zero crossings of the inductor current. If the control quantity is variable, the input stage clamps the control quantity to a control threshold. When in normal mode, the controller stage controls the converter to carry out a phase sequence with timings that depend on the zero crossings and the time quantity, so the converter generates an output current that depends on the time quantity and is prevented from dropping below a minimum current. If the output voltage reaches an upper threshold, the controller stage switches into pulse-skipping mode to suspend the phase sequence, and resumes the phase sequence after the output voltage drops to a lower threshold.

    METHOD OF OPERATING AN ELECTRIC MOTOR, CORRESPONDING DEVICE AND HARD DISK DRIVE

    公开(公告)号:US20230352050A1

    公开(公告)日:2023-11-02

    申请号:US18300806

    申请日:2023-04-14

    CPC classification number: G11B19/2072

    Abstract: A method includes coupling an electric motor in a hard disk drive to a set of driver circuits. Each driver circuit includes a high-side switch and a low-side switch. The high-side switch has a high-side current flow path between a supply node coupled to a supply voltage and a switching node coupled to a winding of the electric motor. The low-side switch has a low-side current flow path between the switching node and ground. Respective conduction currents are generated through the low-side current flow paths, in response to a command to reduce the motor speed by coupling a drive voltage to the control terminals of the low-side switches. An intensity of at least one of the respective conduction currents is sensed. In response to the sensed current intensity exceeding a current intensity threshold, the control terminals of the low-side switches are coupled to respective ones of the switching nodes.

    Voltage regulator circuit and corresponding memory device

    公开(公告)号:US11803202B2

    公开(公告)日:2023-10-31

    申请号:US17933972

    申请日:2022-09-21

    CPC classification number: G05F1/575 H02M3/073 H03K5/05 H03K5/249

    Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.

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