公开(公告)号：US07875959B2

公开(公告)日：2011-01-25

申请号：US11216512

申请日：2005-08-31

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L29/04

CPC classification number: H01L29/045 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first direction and the smaller dimensions in a second, perpendicular direction, with one of the directions being parallel to the direction of carrier movement in the channel and the other direction being perpendicular thereto.

Abstract translation: 通过选择性地施加栅极电极和源极/漏极上的硅化物层来选择性地施加MOSFET的沟道。 硅化物层中的应力选择性地通过使第一方向上的硅化物颗粒的尺寸取向，并且在第二垂直方向上定向较小的尺寸，其中一个方向平行于通道中的载体移动方向，并且 其他方向与其垂直。

公开(公告)号：US07839647B2

公开(公告)日：2010-11-23

申请号：US12346804

申请日：2008-12-30

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: H05K1/00

CPC classification number: H05K3/4641 ,  B82Y10/00 ,  H05K1/056 ,  H05K9/0088 ,  H05K2201/026 ,  H05K2201/0323 ,  Y10S977/70 ,  Y10S977/701 ,  Y10S977/712 ,  Y10S977/734 ,  Y10T428/24116 ,  Y10T428/30 ,  Y10T442/10

Abstract: An insulating film includes a first polymer layer, a second polymer layer and an electromagnetic shielding layer sandwiched between the first polymer layer and the second polymer layer. The electromagnetic shielding layer includes a number of carbon nanotube films that are substantially parallel to the first and second polymer layer. Each of the carbon nanotube films includes a number of carbon nanotubes that are substantially parallel to each other. The insulating film can provide anti-EMI effect in printed circuit boards without employing additional electromagnetic shielding layers.

Abstract translation: 绝缘膜包括第一聚合物层，第二聚合物层和夹在第一聚合物层和第二聚合物层之间的电磁屏蔽层。 电磁屏蔽层包括大致平行于第一和第二聚合物层的多个碳纳米管薄膜。 每个碳纳米管膜包括基本上彼此平行的多个碳纳米管。 绝缘膜可以在印刷电路板中提供抗电磁效应，而不需要额外的电磁屏蔽层。

公开(公告)号：US07807546B2

公开(公告)日：2010-10-05

申请号：US11486889

申请日：2006-07-13

Applicant: Wen-Chin Lee ,  Yee-Chia Yeo

Inventor： Wen-Chin Lee ,  Yee-Chia Yeo

IPC: H01L21/76

CPC classification number: H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjacent the active region and comprises an insulating material. The active region and isolation region form a surface having a step therein. The semiconductor further comprises a dielectric material formed over the step. The dielectric material has a dielectric constant greater than about 8.

Abstract translation: 半导体器件包括衬底。 此外，半导体器件包括有源区和隔离区。 有源区在衬底中并且包括半导体材料。 隔离区也在衬底中，邻近有源区并且包括绝缘材料。 有源区和隔离区形成其中具有台阶的表面。 半导体还包括在该步骤上形成的电介质材料。 电介质材料的介电常数大于约8。

公开(公告)号：US07709903B2

公开(公告)日：2010-05-04

申请号：US11807127

申请日：2007-05-25

Applicant: Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L29/94

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/76844 ,  H01L21/7685 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅极电介质相邻的源极/漏极区域; 源/漏区上的硅化物区; 硅化物区域的顶部和物理接触处的金属层; 金属层上的层间电介质（ILD）; 和ILD的接触开口。 金属层通过接触开口露出。 金属层进一步在ILD下延伸。 半导体结构还包括接触开口中的接触。

公开(公告)号：US20090241333A1

公开(公告)日：2009-10-01

申请号：US12274190

申请日：2008-11-19

Applicant: DONG-QING HE ,  MING WANG ,  YUN-LI ZHU ,  WEN-CHIN LEE

Inventor： DONG-QING HE ,  MING WANG ,  YUN-LI ZHU ,  WEN-CHIN LEE

IPC: H05K3/36

CPC classification number: H05K3/4691 ,  H05K3/386 ,  H05K3/4652 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2203/063 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for manufacturing a printed circuit board (PCB) having different thicknesses in different areas includes: providing a first substrate having two lateral unwanted portions bounded two imaginary boundary lines, a binder layer having a through opening and a second substrate having a mounting area for mounting electronic elements; forming two slots bounded the imaginary boundary lines in an intermediated unwanted portion of the first substrate corresponding to the mounting area; laminating the first and second substrates, and the binder layer with the mounting area exposed via the through opening; filling the two slots and the through opening with a filling material, thereby obtaining a semifinished PCB board; cutting the semifinished PCB board along the imaginary boundary lines to remove the two lateral unwanted portions and a portion of the second substrate corresponding to the two lateral unwanted portions; and removing the intermediate unwanted portion and the filling material.

Abstract translation: 一种用于制造在不同区域中具有不同厚度的印刷电路板（PCB）的方法包括：提供具有限定两个假想边界线的两个横向不需要部分的第一基板，具有通孔的粘合剂层和具有用于 安装电子元件; 在对应于安装区域的第一基板的中间不想要的部分中形成限定虚拟边界线的两个槽; 层叠第一和第二基板和粘合剂层，其中安装区域经由通孔暴露; 用填充材料填充两个槽和通孔，从而获得半成品PCB板; 沿着虚拟边界线切割半成品PCB板，以去除对应于两个横向不需要部分的两个横向不需要部分和第二基板的一部分; 并去除中间不需要的部分和填充材料。

公开(公告)号：US07528044B2

公开(公告)日：2009-05-05

申请号：US11562522

申请日：2006-11-22

Applicant: Wen Chin Lee

Inventor： Wen Chin Lee

IPC: H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L29/78

Abstract: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.

Abstract translation: 公开了一种制造微电子器件的方法，包括用具有不同掺杂剂特性的第一和第二阱形成硅衬底，形成靠近第一阱的第一制剂的第一应变硅 - 锗 - 碳层，以及形成第二应变硅 - 不同于靠近第二孔的第一制剂的第二制剂的锗 - 碳层。 然后形成封盖和绝缘层，栅极结构，间隔物以及源极和漏极，从而产生具有独立应变通道的CMOS器件。

公开(公告)号：US07488428B2

公开(公告)日：2009-02-10

申请号：US11309852

申请日：2006-10-13

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: H01B13/00

CPC classification number: H05K3/0035 ,  H05K3/0038 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/108

Abstract: A method for forming stacked via-holes on a printed circuit board includes the steps of: providing a printed circuit board having a conductive trace formed on a side surface thereof; forming a first copper-clad laminate on the side surface having the conductive trace; forming a number of first copper micro-via in a copper layer of the first copper-clad laminate; forming a second copper-clad laminate on the surface of the copper layer having the first copper micro-via of the first copper-clad laminate; forming a number of second copper micro-via in a copper layer of the second copper-clad laminate by a first laser on the basis of the first copper micro-via, each second copper micro-via being located corresponding to its correspondingly first copper micro-via; and removing corresponding resin layer portions of the first and second copper-clad laminates, using a second laser, to yield the respective stacked via-holes.

Abstract translation: 一种在印刷电路板上形成堆叠的通孔的方法包括以下步骤：提供在其侧表面上形成有导电迹线的印刷电路板; 在具有导电迹线的侧表面上形成第一覆铜层压板; 在第一覆铜层压板的铜层中形成多个第一铜微通孔; 在具有第一覆铜层压板的第一铜微通孔的铜层的表面上形成第二覆铜层压板; 基于第一铜微通孔，通过第一激光在第二覆铜层压板的铜层中形成多个第二铜微通孔，每个第二铜微通孔对应于其相应的第一铜微通孔 -通过; 并使用第二激光器除去第一和第二覆铜层压板的相应树脂层部分，以产生相应的堆叠通孔。

公开(公告)号：US07442967B2

公开(公告)日：2008-10-28

申请号：US11407633

申请日：2006-04-20

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L31/0328

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

Abstract translation: 晶体管包括覆盖沟道区的栅极电介质。 源极区域和漏极区域位于沟道区域的相对侧上。 沟道区由第一半导体材料形成，源极和漏极区由第二半导体材料形成。 栅极电极覆盖栅极电介质。 在栅电极的侧壁上形成一对间隔物。 每个间隔件包括邻近通道区域的空隙。 高应力膜可以覆盖栅电极和间隔物。

公开(公告)号：US20080224227A1

公开(公告)日：2008-09-18

申请号：US11717484

申请日：2007-03-13

Applicant: Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L27/06

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

公开(公告)号：US20080224225A1

公开(公告)日：2008-09-18

申请号：US11717450

申请日：2007-03-13

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7845

Abstract: The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor.

Abstract translation: 第一和第二CMOS晶体管的通道可以选择性地受到压力。 第一晶体管的栅极结构包括在第一晶体管的沟道中产生应力的应力源。 第二晶体管的栅极结构设置成与在第二晶体管的沟道中产生应力的材料层接触。