公开(公告)号：US20100045364A1

公开(公告)日：2010-02-25

申请号：US12496852

申请日：2009-07-02

申请人： Oscar M. K. Law ,  Kong-Beng Thei ,  Harry Chuang

发明人： Oscar M. K. Law ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： G05F3/02

CPC分类号： H03K19/0013

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a frequency detector coupled with a logic circuit; a supply voltage regulator coupled with the frequency detector and designed to provide an adaptive voltage supply to the logic circuit based on a frequency error from the frequency detector; and a substrate bias regulator coupled with the frequency detector and designed to provide an adaptive body bias voltage to the logic circuit based on the frequency error.

摘要翻译： 本发明提供集成电路。 集成电路包括与逻辑电路耦合的频率检测器; 电源电压调节器，与频率检测器耦合，并被设计成基于来自频率检测器的频率误差向逻辑电路提供自适应电压供应; 以及衬底偏置调节器，与所述频率检测器耦合并且被设计成基于所述频率误差向所述逻辑电路提供自适应体偏置电压。

公开(公告)号：US07432179B2

公开(公告)日：2008-10-07

申请号：US11012414

申请日：2004-12-15

申请人： Harry Chuang ,  Kong-Beng Thei

发明人： Harry Chuang ,  Kong-Beng Thei

IPC分类号： H01L21/38

CPC分类号： H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/4966 ,  Y10S438/917

摘要： A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.

摘要翻译： 形成半导体结构的方法包括以下步骤。 在有源区中的衬底上形成栅介电层。 栅极电极层形成在栅极介电层上。 在栅电极层上形成第一光刻胶。 蚀刻栅极电极层和电介质层，从而形成栅极结构和虚拟图案，其中虚拟图案中的至少一个具有活性区域中的至少一部分。 第一个光刻胶被去除。 形成覆盖栅极结构的第二光致抗蚀剂。 去除不受第二光致抗蚀剂保护的虚拟图案。 然后移除第二个光刻胶。

公开(公告)号：US07364957B2

公开(公告)日：2008-04-29

申请号：US11490012

申请日：2006-07-20

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/331

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

公开(公告)号：US20080001188A1

公开(公告)日：2008-01-03

申请号：US11477953

申请日：2006-06-30

申请人： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

发明人： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

摘要翻译： 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

公开(公告)号：US20060188824A1

公开(公告)日：2006-08-24

申请号：US11320513

申请日：2005-12-27

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

IPC分类号： G03F7/00

CPC分类号： H01L23/481 ,  G03F1/144 ,  G03F1/36 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

摘要翻译： 提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。 用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。 该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。 如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。 然后形成照相掩模。 可以使用光掩膜形成半导体结构。

公开(公告)号：US08390072B2

公开(公告)日：2013-03-05

申请号：US13156558

申请日：2011-06-09

申请人： Harry Chuang ,  Kong-Beng Thei ,  Su-Chen Lai ,  Gary Shen

发明人： Harry Chuang ,  Kong-Beng Thei ,  Su-Chen Lai ,  Gary Shen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823828 ,  H01L21/31053 ,  H01L21/823437 ,  H01L29/66545 ,  Y10S438/926

摘要： A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.

摘要翻译： 提供了一种制造半导体器件的方法，其包括提供半导体衬底，形成多个晶体管，每个晶体管具有虚拟栅极结构，在包括虚拟栅极结构的衬底上形成接触蚀刻停止层（CESL），形成 第一电介质层，以填充相邻虚拟栅极结构之间的每个区域的一部分，在CESL和第一介电层上形成化学机械抛光（CMP）阻挡层，在CMP停止层上形成第二介电层，对CMP 所述第二电介质层在所述CMP停止层处基本上停止，并且执行过度抛光以暴露所述伪栅极结构。

公开(公告)号：US08372706B2

公开(公告)日：2013-02-12

申请号：US13218720

申请日：2011-08-26

申请人： Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Provided is a method of fabricating a semiconductor device. A first hard mask layer is formed on a substrate. A second hard mask layer s formed the substrate overlying the first hard mask layer. A dummy gate structure on the substrate is formed on the substrate by using at least one of the first and the second hard mask layers to pattern the dummy gate structure. A spacer element is formed adjacent the dummy gate structure. A strained region on the substrate adjacent the spacer element (e.g., abutting the spacer element). The second hard mask layer and the spacer element are then removed after forming the strained region.

摘要翻译： 提供一种制造半导体器件的方法。 在基板上形成第一硬掩模层。 第二硬掩模层形成覆盖在第一硬掩模层上的基板。 通过使用第一和第二硬掩模层中的至少一个来在衬底上形成伪栅极结构，以对虚拟栅极结构进行图案化。 在虚拟栅极结构附近形成间隔元件。 邻近衬垫元件的衬底上的应变区域（例如，邻接间隔元件）。 然后在形成应变区域之后去除第二硬掩模层和间隔元件。

公开(公告)号：US08361866B2

公开(公告)日：2013-01-29

申请号：US13204461

申请日：2011-08-05

申请人： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

发明人： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

IPC分类号： H01L21/8234

CPC分类号： H01L27/0883 ,  G11C11/412 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S438/919

摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

公开(公告)号：US08304839B2

公开(公告)日：2012-11-06

申请号：US13216114

申请日：2011-08-23

申请人： Kong-Beng Thei ,  Harry Chuang

发明人： Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L27/11

CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation region, wherein the recess is defined by a concave surface of the isolation region; and forming a first gate structure over the substrate surface and a second gate structure over the concave surface of the isolation region.

公开(公告)号：US20120196434A1

公开(公告)日：2012-08-02

申请号：US13443550

申请日：2012-04-10

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L21/02

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。