公开(公告)号：US10249925B2

公开(公告)日：2019-04-02

申请号：US15282086

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Georgios C. Dogiamis ,  Sasha N. Oster ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Richard J. Dischler

IPC: H01P3/12 ,  H01P3/14 ,  H01P11/00 ,  G06F1/18 ,  H01P3/16

Abstract: An apparatus comprises a plurality of waveguides, wherein the waveguides include a dielectric material; an outer shell; and a supporting feature within the outer shell, wherein the waveguides are arranged separate from each other within the outer shell by the supporting feature.

公开(公告)号：US20190096838A1

公开(公告)日：2019-03-28

申请号：US16198429

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Jimin Yao ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.

公开(公告)号：US20190042964A1

公开(公告)日：2019-02-07

申请号：US15925594

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Javier A. Falcon ,  Hubert C. George ,  Shawna M. Liff ,  James S. Clarke

IPC: G06N99/00 ,  B82Y10/00 ,  H01L29/66 ,  H01L23/31 ,  H01L23/00 ,  H01L29/12

CPC classification number: G06N10/00 ,  B82Y10/00 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/82 ,  H01L25/0652 ,  H01L29/127 ,  H01L29/66977

Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.

公开(公告)号：US20180277458A1

公开(公告)日：2018-09-27

申请号：US15992830

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Srikant Nekkanty ,  Joshua D. Heppner ,  Adel A. Elsherbini ,  Yoshihiro Tomita ,  Debendra Mallik ,  Shawna M. Liff ,  Yoko Sekihara

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/66 ,  H01L23/58

Abstract: Devices and methods include an electronic package having a through-mold interconnect are shown herein. Examples of the electronic package include a package assembly. The package assembly including a substrate having a first substrate surface. The first substrate surface including a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block. The contact block including a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block includes a conductive material. The first contact surface is coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package further includes an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block is exposed through the overmold.

公开(公告)号：US10081887B2

公开(公告)日：2018-09-25

申请号：US13715012

申请日：2012-12-14

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Shawna M. Liff ,  Brian S. Doyle ,  Vivek K. Singh

IPC: D03D1/00 ,  D04H13/00 ,  D02G3/44

CPC classification number: D03D1/0088 ,  D02G3/441 ,  D04H13/00 ,  D10B2401/18 ,  Y10T442/3049 ,  Y10T442/3057 ,  Y10T442/3976 ,  Y10T442/603 ,  Y10T442/696

Abstract: Flexible electronically functional fabrics are described that allow for the placement of electronic functionality in flexible substrates such as traditional fabrics. The fabrics can be made using flexible electronically functional fibers or a combination of electronically functional fibers and textile fibers. Electronic devices can be incorporated into the fabric to give it full computing capabilities.

公开(公告)号：US10070520B2

公开(公告)日：2018-09-04

申请号：US14998263

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Joshua D. Heppner ,  Shawna M. Liff ,  Pramod Malatkar

IPC: H05K3/00 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32 ,  A41D1/00 ,  A43B3/00 ,  A41D13/00

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a magnetic particle embedded flexible substrate, a printed flexible substrate for a magnetic tray, or an electro-magnetic carrier for magnetized or ferromagnetic flexible substrates. For instance, in accordance with one embodiment, there are means disclosed for fabricating a flexible substrate having one or more electrical interconnects to couple with leads of an electrical device; integrating magnetic particles or ferromagnetic particles into the flexible substrate; supporting the flexible substrate with a carrier plate during one or more manufacturing processes for the flexible substrate, in which the flexible substrate is held flat against the carrier plate by an attractive magnetic force between the magnetic particles or ferromagnetic particles integrated with the flexible substrate and a complementary magnetic attraction of the carrier plate; and removing the flexible substrate from the carrier plate subsequent to completion of the one or more manufacturing processes for the flexible substrate. Other related embodiments are disclosed.

公开(公告)号：US20180182707A1

公开(公告)日：2018-06-28

申请号：US15389100

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Javier Soto Gonzalez ,  Shawna M. Liff

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1403 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703

Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

公开(公告)号：US20180096862A1

公开(公告)日：2018-04-05

申请号：US15816681

申请日：2017-11-17

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Adel A. Elsherbini ,  Joshua D. Heppner ,  Shawna M. Liff

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L23/315 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/467 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.

公开(公告)号：US09902152B2

公开(公告)日：2018-02-27

申请号：US15199899

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shawna M. Liff ,  Sasha N. Oster ,  Thomas L. Sounart ,  Georgios C. Dogiamis ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: B41J2/14

CPC classification number: B41J2/14298 ,  B41J2/14201 ,  B41J2/14233 ,  B41J2002/14266 ,  B41J2202/13

Abstract: Embodiments of the invention include a piezoelectric package integrated jet device. In one example, the jet device includes a vibrating membrane positioned between first and second cavities of an organic substrate, a piezoelectric material coupled to the vibrating membrane which acts as a first electrode, and a second electrode in contact with the piezoelectric material. The vibrating membrane generates fluid flow through an orifice in response to application of an electrical signal between the first and second electrodes.

公开(公告)号：US20170316880A1

公开(公告)日：2017-11-02

申请号：US15652002

申请日：2017-07-17

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Sasikanth Manipatruni ,  Shawna M. Liff ,  Vivek K. Singh

IPC: H01G4/008 ,  H01L29/06 ,  D03D1/00 ,  B82Y10/00 ,  H01G4/28 ,  H01L49/02 ,  H01L29/775

CPC classification number: H01G4/008 ,  B82Y10/00 ,  D03D1/0088 ,  D10B2401/18 ,  H01G4/28 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/775 ,  Y02E60/13

Abstract: A charge storage fiber is described. In an embodiment, the charge storage fiber includes a flexible electrically conducting fiber, a dielectric coating on the flexible electrically conducting fiber, and a metal coating on the dielectric coating. In an embodiment, the charge storage fiber is attached to a textile-based product.