公开(公告)号：US11282562B2

公开(公告)日：2022-03-22

申请号：US17159706

申请日：2021-01-27

Applicant: Micron Technology, Inc.

Inventor： Stephen Michael Kaminski ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Dale Herber Hiscock ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4091

Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

公开(公告)号：US11244741B1

公开(公告)日：2022-02-08

申请号：US17089002

申请日：2020-11-04

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer

IPC: G11C29/00 ,  G11C11/40 ,  G11C11/408

Abstract: Memory devices are disclosed. A memory device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, and electronic systems are also disclosed.

公开(公告)号：US20210343323A1

公开(公告)日：2021-11-04

申请号：US17319820

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  Sang-Kyun Park ,  Makoto Kitayama

IPC: G11C11/406 ,  G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

公开(公告)号：US20210312961A1

公开(公告)日：2021-10-07

申请号：US16840946

申请日：2020-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Di Wu ,  Debra M. Bell ,  Anthony D. Veches ,  James S. Rehmeyer ,  Libo Wang

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10

Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

公开(公告)号：US20210312310A1

公开(公告)日：2021-10-07

申请号：US16840916

申请日：2020-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Di Wu ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Libo Wang

IPC: G06N5/04 ,  G06N20/00 ,  G06K9/62

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for performing operations associated with machine learning. Machine learning operations may include processing a data set, training a machine learning algorithm, and applying a trained algorithm to a data set. Some of the machine learning operations, such as pattern matching operations, may be performed within a memory device.

公开(公告)号：US11139045B2

公开(公告)日：2021-10-05

申请号：US16693126

申请日：2019-11-22

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer

IPC: G11C7/00 ,  G11C29/44 ,  G11C29/02 ,  G11C29/00 ,  H03M13/11 ,  G11C11/409 ,  H03M13/13 ,  G11C29/18

Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.

公开(公告)号：US20210225433A1

公开(公告)日：2021-07-22

申请号：US17159706

申请日：2021-01-27

Applicant: Micron Technology, Inc.

Inventor： Stephen Michael Kaminski ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Dale Herber Hiscock ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4091

Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

公开(公告)号：US11062755B2

公开(公告)日：2021-07-13

申请号：US16693949

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/00 ,  G11C11/409 ,  G11C11/4074

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

公开(公告)号：US11049565B2

公开(公告)日：2021-06-29

申请号：US15959868

申请日：2018-04-23

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC: G11C16/14 ,  G11C16/30 ,  G11C17/16 ,  G11C17/18 ,  G11C16/22 ,  G11C13/00 ,  G11C11/16 ,  G11C11/22 ,  G11C16/08

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

公开(公告)号：US20210183435A1

公开(公告)日：2021-06-17

申请号：US17187002

申请日：2021-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C11/408

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. A memory device may include a number of memory banks, at least some of which may be simultaneously entered into a refresh mode. A given memory bank may perform an auto-refresh operation or a targeted refresh operation, which may draw less power than the auto-refresh operation. The timing of the targeted refresh operations may be staggered between the refreshing memory banks, such that a portion of the refreshing memory banks are performing a targeted refresh operation simultaneously with a portion of the refreshing memory banks performing an auto-refresh operation.