MEMORY CELL
    132.
    发明申请
    MEMORY CELL 审中-公开
    记忆体

    公开(公告)号:US20090065956A1

    公开(公告)日:2009-03-12

    申请号:US11853358

    申请日:2007-09-11

    IPC分类号: H01L23/48

    摘要: Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the memory cell includes fa first device having a first conductive line extending over a first active region and having a first line end of the first conductive line positioned over an isolation region adjacent to the first active region; and a second device having a second conductive line extending over one of a second active region and a contact element and having a second line end of the second conductive line positioned over the isolation region adjacent to the one of the second active region and the contact element, wherein the first line end and the second line end each include a bulbous end that is distanced from a respective active region or contact element.

    摘要翻译: 公开了形成线端的方法和包括线端的相关存储单元。 在一个实施例中,存储单元包括fa第一器件,其具有在第一有源区上延伸的第一导线,并且第一导线的第一线端位于与第一有源区相邻的隔离区上; 以及第二装置,具有延伸到第二有源区和接触元件之一上的第二导线,并且第二导线的第二线端位于与第二有源区和接触元件中的一个相邻的隔离区上方 ,其中所述第一线端和所述第二线端各自包括与相应的有源区域或接触元件间隔开的球状端。

    Microelectronic circuit structure with layered low dielectric constant regions and method of forming same
    133.
    发明授权
    Microelectronic circuit structure with layered low dielectric constant regions and method of forming same 失效
    具有层状低介电常数区域的微电子电路结构及其形成方法

    公开(公告)号:US07485567B2

    公开(公告)日:2009-02-03

    申请号:US11670524

    申请日:2007-02-02

    IPC分类号: H01L21/4763

    摘要: A method for manufacturing a microelectronic circuit includes the steps of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric material and sacrificial material over the first wiring level; and forming a plurality of interconnect openings and a plurality of gap openings in the alternating layers of layer dielectric material and sacrificial material. The interconnect openings are formed over the first wiring level conductors. The method further includes forming (i) metallic conductors comprising second wiring level conductors, and (ii) interconnects, at the interconnect openings; and removing the layers of the sacrificial material through the gap openings.

    摘要翻译: 一种制造微电子电路的方法包括以下步骤:提供包括由第一布线层介电材料隔开的第一布线层导体的第一布线层; 在所述第一布线层上形成层状介电材料和牺牲材料的多个交替层; 以及在层介电材料和牺牲材料的交替层中形成多个互连开口和多个间隙开口。 互连开口形成在第一布线层导体上。 该方法还包括形成(i)包括第二布线层导体的金属导体,和(ii)互连开口处的互连; 并且通过间隙开口去除牺牲材料的层。

    METHOD FOR IMPROVED PROCESS LATITUDE BY ELONGATED VIA INTEGRATION
    134.
    发明申请
    METHOD FOR IMPROVED PROCESS LATITUDE BY ELONGATED VIA INTEGRATION 审中-公开
    通过整合的改进方法改进方法

    公开(公告)号:US20080284031A1

    公开(公告)日:2008-11-20

    申请号:US12180882

    申请日:2008-07-28

    IPC分类号: H01L23/52

    摘要: Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.

    摘要翻译: 互连双镶嵌结构通过沉积在至少一个介电层的层上制造,掩模形成层用于提供双镶嵌结构的通孔级掩模层; 在通孔级掩模层中形成细长的通孔图案; 沉积一层线路电介质并通过线路级电介质层产生线路图案,并且通过细长通孔电平图案和线路电平图案的投影交点传送线路图案,从而产生对准的双 大马士革结构。 导电衬里层沉积在双镶嵌结构中,然后用导电填充金属填充双镶嵌结构以形成一组金属线。 金属和衬里层被平坦化。