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公开(公告)号：US10096655B1
公开(公告)日：2018-10-09
申请号：US15482016
申请日：2017-04-07
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli
Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
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公开(公告)号：US20180122472A1
公开(公告)日：2018-05-03
申请号：US15841118
申请日：2017-12-13
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Innocenzo Tortorelli , Andrea Redaelli , Fabio Pellizzer
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C13/0097 , G11C2013/0052 , G11C2013/0073 , G11C2013/0092 , G11C2213/73 , G11C2213/76
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.
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公开(公告)号：US09735354B2
公开(公告)日：2017-08-15
申请号：US15153293
申请日：2016-05-12
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Umberto Maria Meotto , Giorgio Servalli
IPC: H01L45/00 , H01L27/24 , H01L23/525
CPC classification number: H01L45/06 , H01L23/5256 , H01L27/2445 , H01L27/2463 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683
Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
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公开(公告)号：US20170229644A1
公开(公告)日：2017-08-10
申请号：US15438499
申请日：2017-02-21
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Umberto M. Meotto
CPC classification number: H01L45/1286 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C13/04 , G11C2013/008 , G11C2213/56 , G11C2213/76 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/1608
Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
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公开(公告)号：US20170104030A1
公开(公告)日：2017-04-13
申请号：US15297925
申请日：2016-10-19
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano
CPC classification number: H01L27/2409 , G11C13/00 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/72 , H01L27/2481 , H01L27/285 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1608
Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.
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Patent Agency Ranking
公开(公告)号：US20160260897A1
公开(公告)日：2016-09-08
申请号：US15153293
申请日：2016-05-12
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Umberto Maria Meotto , Giorgio Servalli
IPC: H01L45/00 , H01L23/525 , H01L27/24
CPC classification number: H01L45/06 , H01L23/5256 , H01L27/2445 , H01L27/2463 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683
Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
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公开(公告)号：US20160211017A1
公开(公告)日：2016-07-21
申请号：US15084103
申请日：2016-03-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Guy C. Wicker , Fabio Pellizzer , Enrico Varesi , Agostino Pirovano
CPC classification number: G11C13/0004 , G11C13/003 , G11C2213/76 , H01L27/2427 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/122 , H01L45/1246 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/1608 , H01L45/1675
Abstract: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely. As a result, current density may be increased at this location, producing heating.
Abstract translation: 相变存储器可以由两个相互垂直间隔的相变材料层形成。 中间电介质可以沿着它们的横向范围的大部分将层彼此间隔开。 可以在中介电介质中提供开口，以允许相变层更接近彼此。 结果，在这个位置可能增加电流密度，产生加热。
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公开(公告)号：US09343676B2
公开(公告)日：2016-05-17
申请号：US14167122
申请日：2014-01-29
Applicant: Micron Technology, Inc.
Inventor： Guy C. Wicker , Fabio Pellizzer , Enrico Varesi , Agostino Pirovano
CPC classification number: G11C13/0004 , G11C13/003 , G11C2213/76 , H01L27/2427 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/122 , H01L45/1246 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/1608 , H01L45/1675
Abstract: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely. As a result, current density may be increased at this location, producing heating.
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公开(公告)号：US09343149B2
公开(公告)日：2016-05-17
申请号：US14328536
申请日：2014-07-10
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Davide Fugazza , Johannes A. Kalb
CPC classification number: G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.
Abstract translation: 本文公开的各种实施例包括用于将存储器阵列的相变存储器（PCM）单元放置在其中在应用随后的SET编程信号之前增强PCM单元的成核概率的温度状态的方法和装置。 在一个实施例中，该方法包括将成核信号施加到PCM单元以在存储器阵列内形成成核位置，其中成核信号具有非零上升沿。 随后施加编程信号以在所述多个PCM单元的选定的单元内实现期望的结晶度。 还描述了附加的方法和装置。
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公开(公告)号：US20150280123A1
公开(公告)日：2015-10-01
申请号：US14738453
申请日：2015-06-12
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Umberto Maria Meotto , Giorgio Servalli
CPC classification number: H01L45/06 , H01L23/5256 , H01L27/2445 , H01L27/2463 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683
Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
Abstract translation: 可以在具有熔丝阵列的同一基板上形成电阻随机存取存储器阵列。 随机存取存储器和熔丝阵列可以使用相同的活性材料。 例如，熔丝阵列和存储器阵列都可以使用硫族化物材料作为有源开关材料。 主阵列可以使用垂直组沟槽隔离的图案，并且熔丝阵列可以仅使用一组平行沟槽隔离。 结果，熔丝阵列可以具有在相邻沟槽隔离之间连续延伸的导电线。 在一些实施例中，该连续线可以减小通过保险丝的导电路径的电阻。
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