公开(公告)号：US12074164B2

公开(公告)日：2024-08-27

申请号：US17815185

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: According to one example, a method includes forming a first set of fin structures on a substrate, forming a sacrificial material between fin structures within the first set of fin structures, forming a dummy gate with a planar bottom surface over the fin structures and the sacrificial material, forming sidewall structures on the dummy gate, laterally etching the sacrificial material underneath the sidewall structures, depositing a lower sidewall structure where the sacrificial material was removed, removing the dummy gate, removing the sacrificial material, and forming a real gate over the fin structures.

公开(公告)号：US12051738B2

公开(公告)日：2024-07-30

申请号：US17666241

申请日：2022-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Li-Yang Chuang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/165

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

公开(公告)号：US12051736B2

公开(公告)日：2024-07-30

申请号：US17463365

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han Chuang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.

公开(公告)号：US20240250032A1

公开(公告)日：2024-07-25

申请号：US18308355

申请日：2023-04-27

Applicant: Taiwan Semiconductor Manufacturing Co,. Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Guan-Lin Chen ,  Yu-Xuan Huang ,  Jin Cai

IPC: H01L23/535 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/535 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.

公开(公告)号：US20240234214A1

公开(公告)日：2024-07-11

申请号：US18615403

申请日：2024-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Wei-Hao Wu ,  Kuo-Cheng Chiang

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/823842 ,  H01L21/32134 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/42372

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

公开(公告)号：US12033899B2

公开(公告)日：2024-07-09

申请号：US18305637

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin Chen ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Shi Ning Ju ,  Jui-Chien Huang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823828 ,  H01L21/02603 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

公开(公告)号：US11990471B2

公开(公告)日：2024-05-21

申请号：US17884694

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L29/42392 ,  H01L29/78696

Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.

公开(公告)号：US11961900B2

公开(公告)日：2024-04-16

申请号：US17328389

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Teng-Chun Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/165 ,  H01L29/7848 ,  H01L2029/7858

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

公开(公告)号：US11916125B2

公开(公告)日：2024-02-27

申请号：US17871509

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

公开(公告)号：US20240030066A1

公开(公告)日：2024-01-25

申请号：US18231076

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Kuan-Ting Pan ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chia-Hao Wang

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/532 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76897 ,  H01L21/02603 ,  H01L21/76805 ,  H01L21/76871 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.