公开(公告)号：US20200058749A1

公开(公告)日：2020-02-20

申请号：US16661108

申请日：2019-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/06

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate having interior surfaces that define a trench within an upper surface of the substrate. One or more dielectric materials are disposed within the trench. A source region disposed within the substrate and a drain region is disposed within of the substrate and separated from the source region along a first direction. A gate structure is over the upper surface of the substrate between the source region and the drain region. The upper surface of the substrate has a first width directly below the gate structure that is larger than a second width of the upper surface of the substrate within the source region or the drain region. The first width and the second width are measured along a second direction that is perpendicular to the first direction.

公开(公告)号：US20200035692A1

公开(公告)日：2020-01-30

申请号：US16587246

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US20190393235A1

公开(公告)日：2019-12-26

申请号：US16430901

申请日：2019-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Feng Teng ,  Wei Cheng Wu

IPC: H01L27/11546 ,  H01L27/11529 ,  H01L27/11524

Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a substrate is provided including a logic region having a plurality of logic sub-regions including a low-voltage logic sub-region and a high-voltage logic sub-region. The method further comprises forming a stack of gate dielectric precursor layers on the plurality of logic sub-regions and removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region and the high-voltage logic sub-region. The method further comprises forming a high-voltage gate dielectric precursor layer on the low-voltage logic sub-region and the high-voltage logic sub-region and removing the high-voltage gate dielectric precursor layer from the low-voltage logic sub-region. The low-voltage logic sub-region has a logic device configured to operate at a voltage smaller than that of another logic device of the high-voltage logic sub-region.

公开(公告)号：US20190393234A1

公开(公告)日：2019-12-26

申请号：US16051721

申请日：2018-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L29/788

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.

公开(公告)号：US20190378905A1

公开(公告)日：2019-12-12

申请号：US16550497

申请日：2019-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming an isolation structure within an upper surface of a substrate. The isolation structure surrounds a continuous region of the substrate defining a source area, a drain area, and a channel area. A gate structure is formed over the channel area. An implantation process is performed to form a source region within the source area and a drain region within the drain area. The channel area is arranged between the source region and the drain region along a first direction and extends past the source region and the drain region along a second direction that is perpendicular to the first direction. The first direction and the second direction are parallel to the upper surface of the substrate.

公开(公告)号：US10475805B2

公开(公告)日：2019-11-12

申请号：US16396963

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/108 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US20190252400A1

公开(公告)日：2019-08-15

申请号：US16396937

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/11573 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

公开(公告)号：US10276587B2

公开(公告)日：2019-04-30

申请号：US15167070

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11573 ,  H01L29/423 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11536

Abstract: The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region. A sacrificial logic gate electrode is formed within the logic region together with a control gate electrode or a select gate electrode within the memory region by patterning a control gate layer or a select gate layer. A first inter-layer dielectric layer is formed between the sacrificial logic gate electrode and the control gate electrode or the select gate electrode. A hard mask is formed over the first inter-layer dielectric layer to cover the memory region and to expose the sacrificial logic gate electrode within the logic region. The sacrificial logic gate electrode is replaced with a high-k gate dielectric layer and a metal layer to form a metal gate electrode within the logic region.

公开(公告)号：US20190067300A1

公开(公告)日：2019-02-28

申请号：US15903770

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC: H01L27/11 ,  H01L23/528 ,  G11C29/08 ,  G06F17/50 ,  G11C29/50

Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

公开(公告)号：US10147794B2

公开(公告)日：2018-12-04

申请号：US15332115

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11568 ,  H01L29/51

Abstract: The present disclosure relates to a split gate memory device. In some embodiments, the split gate memory device includes a memory gate arranged over a substrate, and a select gate arranged over the substrate. An inter-gate dielectric layer is arranged between sidewalls of the memory gate and the select gate that face one another. The inter-gate dielectric layer extends under the memory gate. A first dielectric is disposed above the inter-gate dielectric layer and is arranged between the sidewalls of the memory gate and the select gate.