公开(公告)号：US11715686B2

公开(公告)日：2023-08-01

申请号：US17222225

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chien-Hsun Chen

IPC: H01L23/522 ,  H01L25/16 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

公开(公告)号：US20230223359A1

公开(公告)日：2023-07-13

申请号：US18174784

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/50 ,  H01L25/0652 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1427 ,  H01L2924/1437 ,  H01L2924/3511 ,  H01L2924/19103

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

公开(公告)号：US20230215854A1

公开(公告)日：2023-07-06

申请号：US18182852

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jiun Yi Wu ,  Hsing-Kuo Hsia

IPC: H01L23/538 ,  G02B6/122 ,  H01L23/498 ,  H10B80/00 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  G02B6/122 ,  H01L23/49833 ,  H10B80/00 ,  H01L21/4857 ,  H01L24/29 ,  H01L24/32 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L23/49816 ,  H01L21/4853 ,  H01L2224/16237 ,  H01L2224/13021 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/32225 ,  H01L2224/83102 ,  H01L2224/2919 ,  H01L2924/0635 ,  H01L2224/73204 ,  H01L24/81 ,  H01L24/83

Abstract: An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.

公开(公告)号：US11532582B2

公开(公告)日：2022-12-20

申请号：US17002471

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L23/538 ,  H01L21/02

Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.

公开(公告)号：US11515173B2

公开(公告)日：2022-11-29

申请号：US16869066

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US20220359406A1

公开(公告)日：2022-11-10

申请号：US17869286

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chun-Chih Chuang ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

公开(公告)号：US20220352096A1

公开(公告)日：2022-11-03

申请号：US17813906

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.

公开(公告)号：US20220278087A1

公开(公告)日：2022-09-01

申请号：US17186726

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A method includes forming a redistribution structure on a carrier substrate, coupling a first side of a first interconnect structure to a first side of the redistribution structure using first conductive connectors, where the first interconnect structure includes a core substrate, where the first interconnect structure includes second conductive connectors on a second side of the first interconnect structure opposite the first side of the first interconnect structure, coupling a first semiconductor device to the second side of the first interconnect structure using the second conductive connectors, removing the carrier substrate, and coupling a second semiconductor device to a second side of the redistribution structure using third conductive connectors, where the second side of the redistribution structure is opposite the first side of the redistribution structure.

公开(公告)号：US20220099887A1

公开(公告)日：2022-03-31

申请号：US17340363

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Jiun Yi Wu ,  Hung-Yi Kuo ,  Shang-Yun Hou

IPC: G02B6/12 ,  H01L23/00 ,  H01L31/02 ,  H01L31/0232 ,  H01L25/16 ,  H01L25/18

Abstract: A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

公开(公告)号：US20220093498A1

公开(公告)日：2022-03-24

申请号：US17457728

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66 ,  H05K3/40

Abstract: A method includes forming a first redistribution line, forming a polymer layer including a first portion encircling the first redistribution line and a second portion overlapping the first redistribution line, forming a pair of differential transmission lines over and contacting the polymer layer, and molding the pair of differential transmission lines in a molding compound. The molding compound includes a first portion encircling the pair of differential transmission lines, and a second portion overlapping the pair of differential transmission lines. An electrical connector is formed over and electrically coupling to the pair of differential transmission lines.