公开(公告)号：US20150131848A1

公开(公告)日：2015-05-14

申请号：US14076030

申请日：2013-11-08

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Prasanna Baja Thirumaleshwara ,  Vijaykumar Nagarajan

IPC: G06K9/00 ,  G06K9/62 ,  G06T11/60 ,  G06K9/46

CPC classification number: G06K9/00624 ,  G06K9/4604 ,  G06K9/4642 ,  G06K9/6267 ,  G06K9/6269 ,  G06N99/005 ,  G06T11/60

Abstract: An exemplary object detection method includes generating feature block components representing an image frame, and analyzing the image frame using the feature block components. For each feature block row of the image frame, feature block components associated with the feature block row are evaluated to determine a partial vector dot product for detector windows that overlap a portion of the image frame including the feature block row, such that each detector window has an associated group of partial vector dot products. The method can include determining a vector dot product associated with each detector window based on the associated group of partial vector dot products, and classifying an image frame portion corresponding with each detector window as an object or non-object based on the vector dot product. Each feature block component can be moved from external memory to internal memory once implementing the exemplary object detection method.

Abstract translation: 示例性对象检测方法包括生成表示图像帧的特征块分量，以及使用特征块分量来分析图像帧。 对于图像帧的每个特征块行，评估与特征块行相关联的特征块分量，以确定与包括特征块行的图像帧的一部分重叠的检测器窗口的部分矢量点积，使得每个检测器窗口 具有相关组的部分矢量点积。 该方法可以包括基于相关组的部分矢量点积来确定与每个检测器窗口相关联的矢量点积，并且基于矢量点积将对应于每个检测器窗口的图像帧部分分类为对象或非对象。 一旦实现了示例性对象检测方法，每个特征块组件可以从外部存储器移动到内部存储器。

公开(公告)号：US20150123256A1

公开(公告)日：2015-05-07

申请号：US14072572

申请日：2013-11-05

Applicant: Analog Devices Technology

Inventor： Oliver J Kierse ,  Frank Poucher ,  Michael J. Cusack ,  Padraig L. Fitzgerald ,  Patrick Elebert

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L23/16 ,  H01L23/295 ,  H01L23/31 ,  H01L23/3107 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A stress shield for a plastic integrated circuit package is disclosed. A shield plate is attached by an adhesive to a top surface of an integrated circuit die such that the shield plate covers less than all of the top surface and leaves bond pads exposed. A molding material is applied over the shield plate and the integrated circuit die. The shield plate shields the integrated circuit die from stresses imparted by the molding material.

Abstract translation: 公开了一种塑料集成电路封装的应力屏蔽。 屏蔽板通过粘合剂附接到集成电路管芯的顶表面，使得屏蔽板覆盖小于所有顶表面并且留下暴露的接合焊盘。 将模制材料施加在屏蔽板和集成电路模具上。 屏蔽板屏蔽集成电路模具与模制材料施加的应力。

公开(公告)号：US20150109158A1

公开(公告)日：2015-04-23

申请号：US14057153

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yunzhi Dong ,  Hajime Shibata ,  Wenhua W. Yang ,  Richard E. Schreier

IPC: H03M3/00

CPC classification number: H03M3/344 ,  H03M1/00 ,  H03M1/12 ,  H03M1/144 ,  H03M1/145 ,  H03M3/30 ,  H03M3/416 ,  H04L25/067 ,  H04M1/72519

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (ΔΣ) modulator is provided at the front-end of the MASH ADC, and another full ΔΣ modulator is provided at the back-end of the MASH ADC. The front-end ΔΣ modulator digitizes an analog input signal, and the back-end ΔΣ modulator digitizes an error between the output of the front-end ΔΣ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

Abstract translation: 本公开描述了一种用于将模拟输入信号转换为数字输出信号的改进的多级噪声整形（MASH）模数转换器（ADC）。 特别地，在MASH ADC的前端提供了一个完整的delta-sigma（＆Dgr＆amp; Sgr）调制器，另一个完整的＆Dgr＆amp; 调制器设置在MASH ADC的后端。 前端＆Dgr＆＆ 调制器将模拟输入信号数字化，后端＆Dgr＆amp; 调制器数字化前端＆Dgr＆amp; Sgr的输出之间的误差; 调制器和（原始）模拟输入信号。 在这种配置中，后端调制器将（全）前端调制器的误差数字化，前端的一些设计约束被放宽。 这些设计约束包括热噪声，数字噪声消除滤波器复杂度（前端的量化噪声已经由前端的噪声传递函数形成）和/或非线性。

公开(公告)号：US20150102949A1

公开(公告)日：2015-04-16

申请号：US14052196

申请日：2013-10-11

Applicant: Sanjay Rajasekhar

Inventor： Sanjay Rajasekhar

IPC: H03M1/08

CPC classification number: H03M1/08 ,  H03M1/00 ,  H03M1/0678 ,  H03M1/747 ,  H03M1/785

Abstract: A circuit may include a plurality of primary digital-to-analog (DAC) elements for converting a digital input signal into an analog output signal. A control circuit may control each primary DAC element to switch between a first state and a second state based on the digital input signal to provide the analog output signal at an output representing the digital input signal. A plurality of corrective DAC elements may be coupled in parallel to the plurality of primary DAC elements between the control circuit and the output. The plurality of corrective DAC elements may be controlled to mitigate for intersymbol interference (ISI) due to parasitic capacitance in the primary DAC elements. The plurality of corrective DAC elements may not contribute a direct current to the analog output signal.

Abstract translation: 电路可以包括用于将数字输入信号转换为模拟输出信号的多个主要数模（DAC）元件。 控制电路可以基于数字输入信号来控制每个主DAC元件在第一状态和第二状态之间切换，以在表示数字输入信号的输出端提供模拟输出信号。 多个校正DAC元件可以在控制电路和输出之间并联耦合到多个初级DAC元件。 可以控制多个校正DAC元件以减轻由于初级DAC元件中的寄生电容引起的符号间干扰（ISI）。 多个校正DAC元件可能不向模拟输出信号贡献直流电流。

公开(公告)号：US20150055732A1

公开(公告)日：2015-02-26

申请号：US13971298

申请日：2013-08-20

Applicant: Patrick PRATT

Inventor： Patrick PRATT

IPC: H04L25/08 ,  H04L25/03

CPC classification number: H04L25/08 ,  H03F1/0222 ,  H03F1/0294 ,  H03F3/19 ,  H04L25/03828

Abstract: Embodiments of the present invention may include power amplifier architectures and systems for use in wireless communication systems. The systems may include a first circuit path for receiving an input signal and decomposing the signal into two vector signals using an out-phasing generator, modifying the vectors based on predetermined value limit, amplifying the vectors using power amplifiers, and combining the vectors to provide an amplified output. The system may include a second circuit path for generating an estimate of an envelope of the input signal and using the envelope to modulate the voltage supplies of the power amplifiers when amplifying the vector signals. The system may also include a feedback path for sending information regarding the envelope of the input signal into the out-phasing generator, which may modify the vector signals in response thereto.

Abstract translation: 本发明的实施例可以包括用于无线通信系统的功率放大器架构和系统。 系统可以包括用于接收输入信号的第一电路路径，并且使用外相发生器将信号分解为两个矢量信号，基于预定值限制修改矢量，使用功率放大器来放大矢量，并且组合该矢量以提供 放大输出。 系统可以包括用于产生输入信号的包络的估计的第二电路路径，并且在放大矢量信号时使用包络来调制功率放大器的电压供应。 系统还可以包括用于将关于输入信号的包络的信息发送到定相发生器的反馈路径，其可以响应于此而修改向量信号。

公开(公告)号：US20150035584A1

公开(公告)日：2015-02-05

申请号：US13958141

申请日：2013-08-02

Applicant: Takashi FUJITA

Inventor： Takashi FUJITA

IPC: H03K17/16

CPC classification number: H03K17/165 ,  H03K17/04206 ,  H03K17/163 ,  H03K17/166

Abstract: A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.

Abstract translation: 驱动器可以在两个阶段中在开状态和断开状态之间提供开关的转换。 在第一阶段中，可以控制开关输出端的电压的电压转换速率。 在第二阶段，可以控制开关的电流梯度。 可以基于开关的输出端子处的电压值来进行第一级和第二级之间的转换。

公开(公告)号：US20150028681A1

公开(公告)日：2015-01-29

申请号：US14063636

申请日：2013-10-25

Applicant: Dan LI

Inventor： Dan LI

IPC: H03K17/00

CPC classification number: H03K17/08104 ,  H03F1/223 ,  Y10T307/696

Abstract: A power stage to generate an output voltage at one of a high reference voltage, an intermediate reference voltage and a low reference voltage, including a first switch stage connecting the output terminal to the high reference voltage, comprising a pair of transistors connected in series along their source-to-drain paths, a first transistor coupled to the output terminal and having its gate biased at the intermediate voltage, a second transistor having a gate that receives a first stage control signal that varies between the high reference voltage and the intermediate reference voltage, a second switch stage connecting the output terminal to the intermediate reference voltage, having a gate that receives a second stage control signal that varies among the high reference voltage, intermediate reference voltage and low reference voltage, a third switch stage connecting the output terminal to the low reference voltage, having a pair of transistors connected in series along their source-to-drain paths, a first transistor coupled to the output terminal and having its gate biased at the intermediate voltage, a second transistor having a gate that receives a third stage control signal that varies between the intermediate reference voltage and the low reference voltage.

Abstract translation: 一种功率级，用于在高参考电压，中间参考电压和低参考电压之一产生输出电压，包括将输出端连接到高参考电压的第一开关级，包括串联连接的一对晶体管 其源极到漏极路径，耦合到输出端并且其栅极偏置在中间电压的第一晶体管，具有栅极的第二晶体管，其接收在高参考电压和中间参考之间变化的第一级控制信号 电压，将输出端子连接到中间参考电压的第二开关级，具有接收在高参考电压，中间参考电压和低参考电压之间变化的第二级控制信号的栅极;连接输出端子的第三开关级 到低参考电压，具有沿其源极串联连接的一对晶体管 所述第一晶体管耦合到所述输出端子并且其栅极偏置在所述中间电压，第二晶体管具有接收在所述中间参考电压和所述低参考电压之间变化的第三级控制信号的栅极。

公开(公告)号：US08941522B2

公开(公告)日：2015-01-27

申请号：US13747892

申请日：2013-01-23

Applicant: Italo Carlos Medina Sánchez-Castro

Inventor： Italo Carlos Medina Sánchez-Castro

IPC: H03M1/80 ,  H03M1/78 ,  H03M1/68 ,  H03M1/74 ,  H03M1/76

CPC classification number: H03M1/785 ,  H03M1/687 ,  H03M1/745 ,  H03M1/765

Abstract: A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.

Abstract translation: 数模转换器（DAC）的数字输入被分为最重要的部分和较小的显着部分。 至少一个抽头电压发生器产生多个电压，优选使用电阻串。 解码器解码形成较小有效部分的至少一个子字，以生成对应的至少一个控制信号。 开关单元响应于至少一个控制信号访问由至少一个抽头电压发生器产生的电压。 定标电流发生器从每个访问电压产生相应的加权电流。 输出级将所有加权电流与作为数字输入的最高有效部分的模拟表示的电压组合以产生整个数字输入的模拟近似。

公开(公告)号：US20150022386A1

公开(公告)日：2015-01-22

申请号：US13945647

申请日：2013-07-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Kevin Cao-Van Lam ,  Richard E. Schreier ,  Donald W. Paterson

IPC: H03M1/10

CPC classification number: H03M3/38 ,  H03M1/1009 ,  H03M3/392 ,  H03M3/424 ,  H03M3/454

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by denormalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value. In some embodiments, the integrated circuit further includes a scaling module configured to scale the component value based on scaling parameters.

Abstract translation: 集成电路包括：组件计算器，被配置为从至少一个应用参数计算高可编程模数转换器（ADC）的至少一个分量值;以及映射模块，被配置为将分量值映射到对应的寄存器设置 基于至少一个工艺参数，其中所述集成电路产生能够编程所述ADC的数字控制信号。 在具体实施例中，组件计算器使用应用参数的归一化表示的代数函数来近似评估至少一个归一化的ADC系数。 通过对归一化的ADC系数进行非归一化来进一步计算分量值。 在另一具体实施例中，组件计算器使用应用参数的代数函数来计算组件值。 在一些实施例中，集成电路还包括缩放模块，其被配置为基于缩放参数来缩放分量值。

公开(公告)号：US08912940B2

公开(公告)日：2014-12-16

申请号：US13841150

申请日：2013-03-15

Applicant: Dennis A. Dempsey

Inventor： Dennis A. Dempsey

IPC: H03M1/78 ,  H03M1/08 ,  H03M1/68 ,  H03M1/76

CPC classification number: H03M1/0872 ,  H03M1/682 ,  H03M1/765

Abstract: Embodiments of the present invention may provide a string DAC with charge boosting. The string DAC may include multiple strings, such as an MSB DAC and an LSB DAC, for converting a digital word into a corresponding analog voltage. The string DAC may also include a charge boost system to couple a charge into or out of the DAC during a code transition, such as a MSB code transition. The string DAC may operate in a break-before-make connection technique where all relevant connections are substantially open-circuited before new connections are made. Therefore, the charge boost may shorten the settling time of impedance elements in the string DAC between code transitions and may substantially reduce (or eliminate) glitches.

Abstract translation: 本发明的实施例可以提供具有电荷增压的串联DAC。 串DAC可以包括多个串，例如MSB DAC和LSB DAC，用于将数字字转换成相应的模拟电压。 串DAC还可以包括充电提升系统，以在诸如MSB代码转换的代码转换期间将电荷耦合到DAC中或从DAC中耦合。 串DAC可以在制造前连接技术中进行操作，其中在进行新连接之前所有相关连接基本上都是开路的。 因此，充电提升可以缩短代码转换之间的串DAC中的阻抗元件的建立时间，并且可以显着地减少（或消除）毛刺。