公开(公告)号：US20110076813A1

公开(公告)日：2011-03-31

申请号：US12961167

申请日：2010-12-06

Applicant: Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

Inventor： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

IPC: H01L21/8238

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract translation: 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

公开(公告)号：US20100307561A1

公开(公告)日：2010-12-09

申请号：US12793461

申请日：2010-06-03

Applicant: Benyamin Buller ,  Long Cheng ,  Akhlesh Gupta ,  Anke Abken

Inventor： Benyamin Buller ,  Long Cheng ,  Akhlesh Gupta ,  Anke Abken

IPC: H01L31/042 ,  H01L31/0256 ,  H01L31/0288 ,  H01L31/18

CPC classification number: H01L31/0392 ,  H01L31/03923 ,  H01L31/0749 ,  Y02E10/541 ,  Y02P70/521

Abstract: A photovoltaic device can include a second metal layer adjacent to a first layer, where the first layer is positioned adjacent to a substrate, and where the second metal layer includes a dopant; and a copper-indium-gallium diselenide (CIGS) layer adjacent to the second metal layer.

Abstract translation: 光伏器件可以包括与第一层相邻的第二金属层，其中第一层邻近衬底定位，并且其中第二金属层包括掺杂剂; 和与第二金属层相邻的铜铟镓二硒化物（CIGS）层。

公开(公告)号：US20100130101A1

公开(公告)日：2010-05-27

申请号：US12621376

申请日：2009-11-18

Applicant: YUCHUN WANG ,  Long Cheng ,  Kuo-Lih Chang ,  Wei-Yung Hsu ,  Wen-Chiang Tu

Inventor： YUCHUN WANG ,  Long Cheng ,  Kuo-Lih Chang ,  Wei-Yung Hsu ,  Wen-Chiang Tu

IPC: B24B49/04 ,  B24B49/10 ,  B24B49/12 ,  B24B57/02

CPC classification number: B24B37/042 ,  B24B49/10 ,  B24B49/12 ,  B24B57/02

Abstract: Embodiments described herein provide a method for polishing a substrate surface. The methods generally include storing processing components in multiple storage units during processing, and combining the processing components to create a slurry while flowing the processing components to a polishing pad. A substrate is polished using the slurry, and the thickness of a material layer disposed on the substrate is determined. The flow rate of one or more processing components is then adjusted to affect the rate of removal of the material layer disposed on the substrate.

Abstract translation: 本文所述的实施例提供了一种用于抛光衬底表面的方法。 所述方法通常包括在处理期间将处理组件存储在多个存储单元中，并且将处理组件组合以在将处理组件流动到抛光垫的同时产生浆料。 使用浆料对基材进行研磨，并测定设置在基材上的材料层的厚度。 然后调整一个或多个处理部件的流速以影响设置在基板上的材料层的去除速率。

公开(公告)号：US20100052058A1

公开(公告)日：2010-03-04

申请号：US12401876

申请日：2009-03-11

Applicant: Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

Inventor： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/66545 ,  Y10S438/926

Abstract: A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.

Abstract translation: 公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。 该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

公开(公告)号：US20090273055A1

公开(公告)日：2009-11-05

申请号：US12503641

申请日：2009-07-15

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Abstract translation: 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US20080288529A1

公开(公告)日：2008-11-20

申请号：US11869959

申请日：2007-10-10

Applicant: Long Cheng ,  Yi Fei Fang ,  Liang Qi ,  Yi Zhen Xu ,  Pu Yang

Inventor： Long Cheng ,  Yi Fei Fang ,  Liang Qi ,  Yi Zhen Xu ,  Pu Yang

IPC: G06F7/00

CPC classification number: G06F17/30595

Abstract: Techniques for reconstructing a target hierarchy tree structure from profiling data of a computer system according to a predefined relational model, so as to obtain profiling information of a certain selected node. The predefined relational model is defined in advance according to a hierarchy tree structure of the profiling data, and is stored in an external storage system. The hierarchy tree structures can be constructed dynamically as required, thus the occupied amount of a memory can be seduced and users can view the profiling data freely.

Abstract translation: 用于根据预定义的关系模型从计算机系统的数据分析重建目标层次结构树结构的技术，以便获得特定选定节点的分析信息。 预定义的关系模型根据分析数据的层次结构树结构预先定义，并存储在外部存储系统中。 可以根据需要动态构建层次结构树结构，从而可以引导存储器的占用量，用户可以自由查看分析数据。

公开(公告)号：US20080270102A1

公开(公告)日：2008-10-30

申请号：US12110578

申请日：2008-04-28

Applicant: SHENG LU ,  Qingbo Wang ,  Meng Ye ,  Long Cheng ,  Dong Jun Lan ,  Xing Fang ,  Gang Crl Wang

Inventor： SHENG LU ,  Qingbo Wang ,  Meng Ye ,  Long Cheng ,  Dong Jun Lan ,  Xing Fang ,  Gang Crl Wang

IPC: G06G7/62

CPC classification number: H04L67/22 ,  H04L67/1002 ,  H04L67/327

Abstract: A method and system for correlating out interactions, which occur due to one or a set of specific events, of an application, which is deployed in multiple adjacent tiers in an actual environment is described. First, a simulation environment corresponding to the actual environment is created. Then, specific events are led to the actual environment and the simulation environment. A pattern(s) of interactions, which are related with the specific events, between adjacent tiers in the simulation environment and a large number of interactions between adjacent tiers in the actual environment are obtained. Afterwards, interactions, which are related with the specific events, between adjacent tiers among the obtained interactions between adjacent tiers in the actual environment are correlated using a template of the obtained pattern(s) of interactions, which are related with the specific events, between adjacent tiers in the simulation environment as a template.

Abstract translation: 描述了在实际环境中部署在多个相邻层中的用于将由于一个或一组特定事件而发生的交互相关联的应用的方法和系统。 首先，创建与实际环境对应的仿真环境。 那么具体的事件就会导致实际的环境和模拟环境。 获得与模拟环境中的相邻层之间的特定事件相关的交互模式以及实际环境中相邻层之间的大量交互。 之后，与实际环境中的相邻层之间获得的相互作用之间的相邻层之间的与具体事件相关的交互将使用获得的与特定事件相关的模式的模板相关联，该模板与特定事件相关， 模拟环境中的相邻层作为模板。

公开(公告)号：US20080215922A1

公开(公告)日：2008-09-04

申请号：US12014209

申请日：2008-01-15

Applicant: Long Cheng ,  Ying Chen ,  Dong Jun Lan ,  Qingbo Wang ,  Meng Ye

Inventor： Long Cheng ,  Ying Chen ,  Dong Jun Lan ,  Qingbo Wang ,  Meng Ye

IPC: G06F11/00

CPC classification number: G06F11/3664 ,  G06F11/366

Abstract: A system, method and program enabling users to diagnose applications easily without affecting the operating performance of the application server, optimizing the log mechanism based on the integrated development environment. The method includes running the application in a main running environment and at least one shadow environment, the shadow environment obtained by duplicating the main running environment; and the main running environment interacting with the shadow environment with respect to the fault of the application. The method includes performing the steps of the main running environment: monitoring the exceptions in the system and sending system exception information to the shadow environment in the event of finding exceptions in the system. The shadow environment: receives the system exception information, opens diagnostic log/trace functions to obtain diagnosis log/trace files related to the system exceptions, and analyzes the diagnosis result based on the obtained diagnosis log/trace files.

Abstract translation: 一种系统，方法和程序，使用户能够轻松地诊断应用程序，而不会影响应用程序服务器的运行性能，基于集成开发环境优化日志机制。 该方法包括在主运行环境和至少一个影子环境中运行应用程序，通过复制主运行环境获得的影子环境; 以及与应用程序故障相关的主要运行环境与影子环境相互作用。 该方法包括执行主要运行环境的步骤：在发现系统异常的情况下，监视系统中的异常并将系统异常信息发送到影子环境。 影子环境：接收系统异常信息，打开诊断日志/跟踪功能，获取与系统异常相关的诊断日志/跟踪文件，并根据获取的诊断日志/跟踪文件分析诊断结果。

公开(公告)号：US20080179688A1

公开(公告)日：2008-07-31

申请号：US12058997

申请日：2008-03-31

Applicant: Kong Beng Thei ,  Chung Long Cheng ,  Harry Chuang

Inventor： Kong Beng Thei ,  Chung Long Cheng ,  Harry Chuang

IPC: H01L29/78

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

Abstract translation: 公开了一种具有改善的源极/漏极结的半导体器件和用于制造该器件的方法。 优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域 形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。 在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度与45度之间。 另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。

公开(公告)号：US07298011B2

公开(公告)日：2007-11-20

申请号：US11215103

申请日：2005-08-30

Applicant: Kong-Beng Thei ,  Chung-Long Cheng ,  Harry Chuang

Inventor： Kong-Beng Thei ,  Chung-Long Cheng ,  Harry Chuang

IPC: H01L29/94

CPC classification number: H01L29/6656 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/66507 ,  H01L29/6653

Abstract: A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.

Abstract translation: 具有凹入的L形间隔物的半导体器件及其制造方法。 凹进的L形间隔件包括垂直部分和水平部分。 垂直部分设置在导体图案的下侧壁上，露出其上侧壁。 顶部间隔物在L形间隔件上，其中L形间隔件的垂直部分与顶部间隔物的宽度比为至少约2:1。