公开(公告)号：US20070189100A1

公开(公告)日：2007-08-16

申请号：US11443028

申请日：2006-05-31

申请人： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

发明人： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1006

摘要： A memory cell array ARY includes a plurality of sub-arrays SARY. A data transfer unit DTU alternately accesses the sub-arrays SARY to transfer data between the sub-arrays SARY. Accordingly, it is possible to transfer data stored in one of the sub-arrays SARY to another sub-array SARY without outputting the data to a bus connected to a semiconductor memory MEM. For example, a microcontroller CNT in a system MSYS can use the bus during the data transfer since the bus is not used for the data transfer. As a result, it is possible to prevent the performance of the system MSYS from being deteriorated due to the data transfer.

摘要翻译： 存储单元阵列ARY包括多个子阵列SARY。 数据传输单元DTU交替地访问子阵列SARY以在子阵列SARY之间传送数据。 因此，可以将存储在一个子阵列SARY中的数据传送到另一个子阵列SARY，而不将数据输出到连接到半导体存储器MEM的总线。 例如，系统MSYS中的微控制器CNT可以在数据传输期间使用总线，因为总线不用于数据传输。 结果，可以防止系统MSYS的性能由于数据传输而恶化。

公开(公告)号：US20070189052A1

公开(公告)日：2007-08-16

申请号：US11443030

申请日：2006-05-31

申请人： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

发明人： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

IPC分类号： G11C13/04 ,  G11C7/10 ,  G11C5/06

CPC分类号： G06F13/4243 ,  G11C5/066 ,  G11C7/1006

摘要： A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.

摘要翻译： 存储器控制器将每个由多个位组成的访问信号复用为光信号并输出​​复用的光信号。 此时，产生根据存储器件波长不同的光信号。 存储器接口单元将复用的光信号解复用为原始光信号，并将解复用的光信号转换为电信号。 存储器接口单元根据解复用的光信号的波长来确定应该向哪个存储器件输出由转换产生的电信号。 这使得存储器控制器不需要向存储器接口单元发送用于识别存储器件的信号。 存储器接口单元不需要包括用于识别存储器件的解码电路。

公开(公告)号：US07165159B2

公开(公告)日：2007-01-16

申请号：US10687591

申请日：2003-10-20

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G06F13/36

CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

摘要： A memory controller converts controller output signals output from a controller int memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

摘要翻译： 存储器控制器根据存储器芯片的操作规范将来自控制器输出的控制器输出信号转换为存储器输入信号以进行操作，并通过公共总线将结果输出到存储器芯片。 存储器控制器还通过公共总线接收从存储器芯片输出的存储器输出信号，并将接收的信号转换成可接收到控制器的控制器输入信号。 这允许单个存储器控制器访问多种类型的存储器芯片。 结果，存储器控制器可以减小芯片尺寸，降低存储器系统的成本。

公开(公告)号：US06650593B2

公开(公告)日：2003-11-18

申请号：US10057989

申请日：2002-01-29

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C700

CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

摘要翻译： 存储器控制器根据要操作的存储器芯片的操作规范，将从控制器输出的控制器输出信号转换为存储器输入信号，并通过公共总线将结果输出到存储器芯片。 存储器控制器还通过公共总线接收从存储器芯片输出的存储器输出信号，并将接收的信号转换成可接收到控制器的控制器输入信号。 这允许单个存储器控制器访问多种类型的存储器芯片。 结果，存储器控制器可以减小芯片尺寸，降低存储器系统的成本。

公开(公告)号：US6026041A

公开(公告)日：2000-02-15

申请号：US22403

申请日：1998-02-12

申请人： Takaaki Suzuki ,  Hiroyuki Kobayashi ,  Toyomitsu Matsumoto ,  Masao Taguchi ,  Yoshihiro Takemae

发明人： Takaaki Suzuki ,  Hiroyuki Kobayashi ,  Toyomitsu Matsumoto ,  Masao Taguchi ,  Yoshihiro Takemae

IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C7/22 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C11/406 ,  G11C7/12

摘要： A semiconductor memory device includes a memory part which stores data, a decoder which decodes a command externally supplied to the semiconductor memory device, and a precharge protection circuit which dynamically determines, based on the command decoded by the decoder, a period necessary to precharge a predetermined circuit part of the semiconductor memory device, so that a precharge operation on the predetermined circuit part can be protected.

摘要翻译： 一种半导体存储器件包括存储数据的存储器部分，对外部提供给半导体存储器件的指令进行解码的解码器，以及预充电保护电路，其基于解码器解码的命令动态地确定预充电所需的时间 半导体存储器件的预定电路部分，从而可以保护对预定电路部分的预充电操作。

公开(公告)号：US5867438A

公开(公告)日：1999-02-02

申请号：US726168

申请日：1996-10-04

申请人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

发明人： Yukihiro Nomura ,  Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

摘要： A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

摘要翻译： 具有多个存储单元的DRAM（动态随机存取存储器）包括读取或写入存储单元的数据的数据读/写电路，刷新存储在存储单元中的数据的自刷新电路，以及供给单元 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。

公开(公告)号：US5737263A

公开(公告)日：1998-04-07

申请号：US688740

申请日：1996-07-31

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C7/067 ,  G11C11/4074 ,  G11C11/4091

摘要： A semiconductor memory has a plurality of bit lines, a plurality of word lines, a plurality of memory cells, a power source unit, and a plurality of sense amplifiers. The memory cells are formed at intersection portions of the bit lines and the word lines, and each of the memory cells includes a transistor and a capacitor. The power source unit is connected to the capacitors of the memory cells. Each of the sense amplifiers, which is connected to a corresponding one of the bit lines and the power source, is used to amplify a voltage between a potential of the corresponding bit line. This memory realizes high integration, large capacity, and low power consumption.

摘要翻译： 半导体存储器具有多个位线，多个字线，多个存储单元，电源单元和多个读出放大器。 存储单元形成在位线和字线的交叉部分，并且每个存储单元包括晶体管和电容器。 电源单元连接到存储单元的电容器。 连接到相应的一个位线和电源的每个读出放大器用于放大对应位线的电位之间的电压。 该存储器实现了高集成度，大容量和低功耗。

公开(公告)号：US5568427A

公开(公告)日：1996-10-22

申请号：US433255

申请日：1995-05-02

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1072

摘要： A memory and a method for reading out of memory including a register for holding one row of data of a memory cell array, a plurality of first switching transistors for switching ON/OFF between a plurality of bit lines and the corresponding bits in the register, a plurality of second switching transistors for switching ON/OFF between the bit lines and a pair of data bus lines and a plurality of third switching transistors for switching ON/OFF between the data bus lines and the bits in the register. In random access of memory cells, selection and control is performed for the plurality of second switching transistors with an output of a column decoder. In sequential reading out of the register, one row data of the memory cells selected by a row decoder are written in the register by controlling the plurality of first switching transistors and with an output of the column decoder, sequential selection and control of the plurality of third switching transistors is performed.

摘要翻译： 一种用于读出存储器的存储器和方法，包括用于保持存储单元阵列的一行数据的寄存器，用于在多个位线之间切换ON / OFF的多个第一开关晶体管和寄存器中的相应位， 多个第二开关晶体管，用于在位线和一对数据总线之间切换ON / OFF;以及多个第三开关晶体管，用于在数据总线之间切换ON / OFF以及寄存器中的位。 在存储器单元的随机存取中，利用列解码器的输出对多个第二开关晶体管执行选择和控制。 在顺序读出寄存器中，由行解码器选择的存储单元的一行数据通过控制多个第一开关晶体管并通过列解码器的输出被写入寄存器，对多个 执行第三开关晶体管。

公开(公告)号：US5499213A

公开(公告)日：1996-03-12

申请号：US83443

申请日：1993-06-29

申请人： Makoto Niimi ,  Shigemasa Ito ,  Toyonobu Yamada ,  Yoshihiro Takemae ,  Yoshiharu Kato

发明人： Makoto Niimi ,  Shigemasa Ito ,  Toyonobu Yamada ,  Yoshihiro Takemae ,  Yoshiharu Kato

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.

摘要翻译： 半导体存储器件具有用于产生刷新脉冲的振荡器单元，刷新地址检测单元，用于检测刷新的地址并在完成所有地址的刷新时输出预定信号;以及输出控制单元，用于继续自刷新模式 在响应于外部信号释放自刷新模式之前，根据刷新地址检测单元的信号刷新所有地址。 因此，继续刷新操作直到所有单元被刷新，从而存储在半导体存储器件中的数据不会丢失并被正确地刷新。

公开(公告)号：US4799196A

公开(公告)日：1989-01-17

申请号：US17652

申请日：1987-02-24

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C11/404 ,  G11C11/00 ,  G11C11/40 ,  G11C11/401 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C11/4097 ,  G11C11/005

摘要： A semiconductor memory device including a plurality of word lines and a plurality of bit lines; a plurality of memory cells connected between one of the word lines and one of the bit lines, at least one of the memory cells connected to the word lines being of a first type having an N channel type transfer gate transistor, at least one of the memory cells connected to the word lines being of a second type having a P channel type transfer gate transistor; and means for applying a selection signal to a selected word line, the selection signal having one of two opposite polarities in accordance with an access to the first type memory cells and an access to the second type memory cells.

摘要翻译： 一种包括多个字线和多个位线的半导体存储器件; 多个存储单元，连接在一个字线和一个位线之间，连接到字线的存储单元中的至少一个是具有N沟道型转移栅极晶体管的第一类型，至少一个 连接到字线的存储单元是具有P沟道型转移栅晶体管的第二类型; 以及用于将选择信号施加到所选择的字线的装置，所述选择信号根据对所述第一类型存储器单元的访问和对所述第二类型存储单元的存取而具有两个相反极性之一。