公开(公告)号：US6026041A

公开(公告)日：2000-02-15

申请号：US22403

申请日：1998-02-12

申请人： Takaaki Suzuki ,  Hiroyuki Kobayashi ,  Toyomitsu Matsumoto ,  Masao Taguchi ,  Yoshihiro Takemae

发明人： Takaaki Suzuki ,  Hiroyuki Kobayashi ,  Toyomitsu Matsumoto ,  Masao Taguchi ,  Yoshihiro Takemae

IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C7/22 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C11/406 ,  G11C7/12

摘要： A semiconductor memory device includes a memory part which stores data, a decoder which decodes a command externally supplied to the semiconductor memory device, and a precharge protection circuit which dynamically determines, based on the command decoded by the decoder, a period necessary to precharge a predetermined circuit part of the semiconductor memory device, so that a precharge operation on the predetermined circuit part can be protected.

摘要翻译： 一种半导体存储器件包括存储数据的存储器部分，对外部提供给半导体存储器件的指令进行解码的解码器，以及预充电保护电路，其基于解码器解码的命令动态地确定预充电所需的时间 半导体存储器件的预定电路部分，从而可以保护对预定电路部分的预充电操作。

公开(公告)号：US5767712A

公开(公告)日：1998-06-16

申请号：US892066

申请日：1997-07-14

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

IPC分类号： G06F1/04 ,  G11C7/22 ,  H01L27/02 ,  H03K3/356 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/24 ,  H03L7/00

CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K3/356113 ,  H03K3/356156 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/249

摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

摘要翻译： 一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间 根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟的周期时间获得特定时间 信号，以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

公开(公告)号：US06166992A

公开(公告)日：2000-12-26

申请号：US517338

申请日：2000-03-02

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

IPC分类号： G06F1/04 ,  G11C7/22 ,  H01L27/02 ,  H03K3/356 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/24 ,  G11C8/00

CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K3/356113 ,  H03K3/356156 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/249

摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

摘要翻译： 一种半导体器件包括：单触发脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟的周期时间 来自单触发脉冲发生电路输出的单触发脉冲的信号;内部时钟发生电路，其基于由周期时间测量电路测量的周期时间和从一个脉冲发生电路输出的单次脉冲产生第二时钟信号 -shot脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间 时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

公开(公告)号：US6078514A

公开(公告)日：2000-06-20

申请号：US61023

申请日：1998-04-16

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Takaaki Suzuki ,  Hiroyoshi Tomita ,  Toshiya Uchida ,  Yasuharu Sato ,  Atsushi Hatakeyama ,  Masato Matsumiya ,  Yasurou Matsuzaki

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Takaaki Suzuki ,  Hiroyoshi Tomita ,  Toshiya Uchida ,  Yasuharu Sato ,  Atsushi Hatakeyama ,  Masato Matsumiya ,  Yasurou Matsuzaki

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L21/60 ,  H01L25/00 ,  H01L27/10 ,  H01L25/04 ,  H01L23/36

CPC分类号： H01L23/60 ,  G11C7/1006 ,  G11C7/22 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L24/48 ,  H01L27/0266 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/30105

摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

摘要翻译： 半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。 所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的 逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是 沿着至少一个存储器芯片的一侧布置。

公开(公告)号：US6009039A

公开(公告)日：1999-12-28

申请号：US14976

申请日：1998-01-28

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Takaaki Suzuki ,  Junji Ogawa ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki ,  Hideaki Kawai

IPC分类号： G06F1/04 ,  G11C7/22 ,  H03K3/356 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/24 ,  G11C8/00 ,  G11C16/04

CPC分类号： G11C7/222 ,  G06F1/04 ,  G11C7/22 ,  H03K3/356113 ,  H03K3/356156 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/249 ,  G11C7/04

摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

摘要翻译： 一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间 根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间 时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

公开(公告)号：US06744300B2

公开(公告)日：2004-06-01

申请号：US10277707

申请日：2002-10-23

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H01J1982

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US06498524B1

公开(公告)日：2002-12-24

申请号：US09706731

申请日：2000-11-07

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： H03L708

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US06492846B1

公开(公告)日：2002-12-10

申请号：US09474702

申请日：1999-12-29

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H03K300

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By this constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过这种结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US06298004B1

公开(公告)日：2001-10-02

申请号：US08892790

申请日：1997-07-15

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US06707325B2

公开(公告)日：2004-03-16

申请号：US10278080

申请日：2002-10-23

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H03K300

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.