公开(公告)号：US11177226B2

公开(公告)日：2021-11-16

申请号：US16450266

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC: H01L23/60 ,  H01L23/48 ,  H01L25/07 ,  H01L25/11 ,  H01L25/065

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.

公开(公告)号：US11133261B2

公开(公告)日：2021-09-28

申请号：US15845336

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Chee Kheong Yoon ,  Jia Yan Go

IPC: H01L23/538 ,  H01L25/10 ,  H05K1/18 ,  H01L25/00 ,  H01L25/18 ,  H01L23/18 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

Abstract: An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.

公开(公告)号：US11006514B2

公开(公告)日：2021-05-11

申请号：US16481043

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Jia Yan Go ,  Min Suet Lim ,  Tin Poay Chuah ,  Seok Ling Lim ,  Howe Yin Loo

IPC: H01L23/552 ,  H05K1/02 ,  H01L21/50 ,  H01L23/498 ,  H01L25/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H01L49/02 ,  H01L23/64

Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).

公开(公告)号：US10957649B2

公开(公告)日：2021-03-23

申请号：US16329080

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong

IPC: H01L23/48 ,  H01L23/538 ,  H01L29/06 ,  H01L23/00 ,  H01L25/065 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498

Abstract: A system in package device includes an overpass die on a package substrate and the overpass die includes a recess on the back side in order to straddle a landed die also on the package substrate. The recess is bounded by at least two overpass walls. Communication between the dice is done with a through-silicon via and communication between the overpass die and the package substrate is also done with a through-silicon via.

公开(公告)号：US20190364702A1

公开(公告)日：2019-11-28

申请号：US16535766

申请日：2019-08-08

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Yew San Lim ,  Jia Yan Go ,  Tin Poay Chuah ,  Eng Huat Goh

IPC: H05K9/00 ,  H05K1/11 ,  H05K3/46

Abstract: Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.

公开(公告)号：US20190304914A1

公开(公告)日：2019-10-03

申请号：US16284218

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Boon Ping Koh ,  Eng Huat Goh ,  Jiun Hann Sir ,  Khang Choong Yong ,  Min Suet Lim ,  Wil Choon Song

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.

公开(公告)号：US20190287872A1

公开(公告)日：2019-09-19

申请号：US15925429

申请日：2018-03-19

Applicant: INTEL CORPORATION

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

公开(公告)号：US20190051642A1

公开(公告)日：2019-02-14

申请号：US16146445

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Maruti Gupta Hyde ,  Nageen Himayat ,  Linda Hurd ,  Min Suet Lim ,  Van Le ,  Gayathri Jeganmohan ,  Ankitha Chandran

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/367 ,  G06F1/32 ,  G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit.

公开(公告)号：US10036187B2

公开(公告)日：2018-07-31

申请号：US14996568

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Chung Peng Jackson Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  G06F1/16 ,  G06F1/32 ,  E05D11/00 ,  H05K5/02

Abstract: An apparatus is provided including a docking device to accept a computing device, the docking device including a keyboard and a hinge to connect the computing device to the keyboard, the hinge is configured to allow the computing device, when connected to the hinge, to rotate relative to the keyboard in a laptop orientation. The hinge includes a plurality of interlinked parallel hinge segments at least partially enclosed in a flexible covering, and each hinge segment is to rotate about a respective one of a plurality of parallel axes of the hinge.

公开(公告)号：US10000953B2

公开(公告)日：2018-06-19

申请号：US14996568

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Chung Peng Jackson Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  G06F1/16 ,  G06F1/32 ,  E05D11/00 ,  H05K5/02

Abstract: An apparatus is provided including a docking device to accept a computing device, the docking device including a keyboard and a hinge to connect the computing device to the keyboard, the hinge is configured to allow the computing device, when connected to the hinge, to rotate relative to the keyboard in a laptop orientation. The hinge includes a plurality of interlinked parallel hinge segments at least partially enclosed in a flexible covering, and each hinge segment is to rotate about a respective one of a plurality of parallel axes of the hinge.