公开(公告)号：US11189561B2

公开(公告)日：2021-11-30

申请号：US16574447

申请日：2019-09-18

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Dominik Metzler ,  John Arnold

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

公开(公告)号：US11177213B2

公开(公告)日：2021-11-16

申请号：US16774922

申请日：2020-01-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Tianji Zhou ,  Ashim Dutta ,  Saumya Sharma

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

Abstract: An anti-fuse device having enhanced programming efficiency is provided. The anti-fuse device includes via contact structures that have different critical dimensions located between a first electrode and a second electrode. Notably, a first via contact structure having a first critical dimension is provided between a pair of second via contact structures having a second critical dimension that is greater than the first critical dimension. When a voltage is applied to the device, dielectric breakdown will occur first through the first via contact structure having the first critical dimension.

公开(公告)号：US11158786B2

公开(公告)日：2021-10-26

申请号：US16582762

申请日：2019-09-25

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Lijuan Zou ,  John Arnold

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22

Abstract: Controlled IBE techniques for MRAM stack patterning are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cells using IBE landing on the dielectric while dynamically adjusting an etch time to compensate for variations in a thickness of the MRAM stack, wherein each of the memory cells includes a bottom electrode, an MTJ, and a top electrode; removing foot flares from the bottom electrode of the memory cells which are created during the patterning of the MRAM stack; removing residue from sidewalls of the memory cells which includes metal redeposited during the patterning of the MRAM stack and during the removing of the foot flares; and covering the memory cells in a dielectric encapsulant. An MRAM device is also provided.

公开(公告)号：US11152261B2

公开(公告)日：2021-10-19

申请号：US16664830

申请日：2019-10-26

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  John Arnold ,  Dominik Metzler

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532

Abstract: Techniques for self-aligned top via formation at line ends are provided. In one aspect, a method of forming self-aligned vias at line ends includes: patterning (even/odd) metal lines including using a (first/second) hardmask; cutting the hardmask and a select metal line, even or odd, using a cut mask having a window that exposes the hardmask over a cut region of the select metal line; enlarging the window to expose the hardmask on either side of the cut region; selectively etching the hardmask using the enlarged window to form a T-shaped cavity within the cut region; filling the T-shaped cavity with a gap fill dielectric; removing the hardmask; and recessing the metal lines, wherein the gap fill dielectric overhangs portions of the select metal line that, by the recessing, form the self-aligned vias at ends of the metal lines. A structure is also provided.

公开(公告)号：US20210226120A1

公开(公告)日：2021-07-22

申请号：US16748738

申请日：2020-01-21

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saba Zare ,  Michael Rizzolo ,  Theodorus E. Standaert ,  Daniel C. Edelstein

IPC: H01L43/12

Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.

公开(公告)号：US20210225774A1

公开(公告)日：2021-07-22

申请号：US16744960

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Ashim Dutta

IPC: H01L23/532 ,  H01L23/522 ,  H01L43/08 ,  H01L27/11597 ,  H01L45/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L27/24

Abstract: Re-depositing of metal-containing particles of an embedded electrically conductive structure onto sidewalls of an overlying metal-containing structure is alleviated in the present application by providing a pedestal structure between the embedded electrically conductive structure and the metal-containing structure, wherein the pedestal structure has a flared sidewall that extends beyond a perimeter of the embedded electrically conductive structure. Such a pedestal structure (which can be referred to herein as a footing flare pedestal structure) mitigates, and in some embodiments, entirely eliminates, the exposure of the embedded electrically conductive structure during the patterning of metal-containing layers formed atop the embedded electrically conductive structure.

公开(公告)号：US20210151377A1

公开(公告)日：2021-05-20

申请号：US16685192

申请日：2019-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chi-Chun Liu ,  John C. Arnold ,  Dominik Metzler ,  Nelson Felix ,  Ashim Dutta

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/762

Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.

公开(公告)号：US10957850B2

公开(公告)日：2021-03-23

申请号：US16151401

申请日：2018-10-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Isabel Cristina Chu ,  Son Nguyen ,  Michael Rizzolo ,  John C. Arnold

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: A method for fabricating a semiconductor device includes forming a first encapsulation layer along the device, including forming the first encapsulation layer along a memory device region associated with a memory device, forming an intermediate layer on the first encapsulation layer to enable etch endpoint detection and endpoint-based process control for encapsulation layer etch back, and forming a second encapsulation layer on the intermediate layer.

公开(公告)号：US20200272045A1

公开(公告)日：2020-08-27

申请号：US16282005

申请日：2019-02-21

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Luciana Meli Thompson ,  Ashim Dutta ,  Ekmini A. De Silva

IPC: G03F1/22 ,  H01L21/308 ,  G03F7/075

Abstract: Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.

公开(公告)号：US20200227313A1

公开(公告)日：2020-07-16

申请号：US16245033

申请日：2019-01-10

Applicant: International Business Machines Corporation

Inventor： Kisik Choi ,  Koichi Motoyama ,  Ashim Dutta ,  Iqbal R. Saraf ,  Benjamin D. Briggs

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/02

Abstract: Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.