中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

162 records (took 0.033 seconds)

    Configuring optimal bus turnaround cycles for master-driven serial buses
    141.
    发明授权
    Configuring optimal bus turnaround cycles for master-driven serial buses 有权

    公开(公告)号：US10445270B2

    公开(公告)日：2019-10-15

    申请号：US15994754

    申请日：2018-05-31

    Applicant: QUALCOMM Incorporated

    Inventor： Elisha Ulmer ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F3/06 ,  G06F13/362

    Abstract: Systems, methods, and apparatus for optimizing bus turnaround in a master-driven serial bus are described. A method performed at a master device coupled to a serial bus includes configuring slave devices coupled to the serial bus with respective delay values that define bus turnaround wait periods, transmitting a first read command directed to a first slave device, receiving data after a first wait period initiated after the first read command has been sent, the first wait period being defined by a delay value configured in the first slave device, transmitting a second read command directed to a second slave device, and receiving data after a second wait period initiated after the second read command has been sent, the second wait period being defined by a delay value configured in the second slave device. The first wait period and the second wait period may have different durations.

    IN-DATAGRAM CRITICAL-SIGNALING USING PULSE-COUNT-MODULATION FOR I3C BUS
    142.
    发明申请
    IN-DATAGRAM CRITICAL-SIGNALING USING PULSE-COUNT-MODULATION FOR I3C BUS 审中-公开

    公开(公告)号：US20190238362A1

    公开(公告)日：2019-08-01

    申请号：US15882494

    申请日：2018-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Radu Pitigoi-Aron

    IPC: H04L12/40 ,  H04L25/49 ,  G06F13/42 ,  H04L1/16

    Abstract: Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.

    Dynamic data-link selection over common physical interface
    145.
    发明授权
    Dynamic data-link selection over common physical interface 有权

    公开(公告)号：US10241953B2

    公开(公告)日：2019-03-26

    申请号：US15228877

    申请日：2016-08-04

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian

    IPC: G06F13/42 ,  G06F13/38

    Abstract: A hybrid virtual general purpose input/output (VGI) architecture is provided including a pair of devices coupled through a high-speed cable. The architecture enables a device to communicate sideband signals through the high-speed cable using two pins coupled to respective interconnects of a bus. In an aspect, the architecture may implement link selection without protocol consolidation where the device may configure the two pins for I2C (or I3C) signaling or VGI signaling. In another aspect, the architecture may implement link bridging with protocol consolidation where the device may transmit (or receive) I2C (or I3C) signals through the high-speed cable using a VGI communication protocol.

    Enhanced serial peripheral interface with hardware flow-control
    146.
    发明授权
    Enhanced serial peripheral interface with hardware flow-control 有权

    公开(公告)号：US10140243B2

    公开(公告)日：2018-11-27

    申请号：US15348435

    申请日：2016-11-10

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F9/4401 ,  G06F13/364 ,  G06F13/40

    Abstract: Systems, methods, and apparatus for implementing hardware flow control between devices coupled through a serial peripheral interface. A method for transmitting information using a serial peripheral interface includes initiating an exchange of data over one or more data lines of a serial peripheral interface bus by asserting a first voltage state on a slave select line, transmitting data and clock signals over the serial peripheral interface bus while the slave select line remains at the first voltage state, refraining from transmitting data and clock signals over the serial peripheral interface bus when the slave select line transitions to a second first voltage state, receiving data at a slave device into a receive buffer while the slave select line remains at the first voltage state, and asserting the second voltage state on the slave select line when occupancy of the receive buffer reaches or exceeds a threshold occupancy level.

    Dynamically adjustable multi-line bus shared by multi-protocol devices
    148.
    发明授权
    Dynamically adjustable multi-line bus shared by multi-protocol devices 有权

    公开(公告)号：US10007628B2

    公开(公告)日：2018-06-26

    申请号：US14728777

    申请日：2015-06-02

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

    IPC: G06F13/00 ,  G06F13/364 ,  G06F13/42

    CPC classification number: G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F13/4295

    Abstract: A device is provided that has a bus including a first line and a second line. A first set of devices are coupled to the bus and, in a first mode of operation, configured to use the first line for data transmissions and use the second line for a first clock signal. One or more additional lines are connected between two or more of the devices in the first set of devices for transmitting signaling between the two or more devices. A second set of devices are configured to use the bus and at least one of the additional lines for data transmissions in a second mode of operation, where in the second mode of operation symbols are encoded across the first line, the second line, and the at least one of the additional lines.

    HARD RESET OVER I3C BUS
    149.
    发明申请
    HARD RESET OVER I3C BUS 审中-公开

    公开(公告)号：US20180173667A1

    公开(公告)日：2018-06-21

    申请号：US15658883

    申请日：2017-07-25

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F1/32

    CPC classification number: G06F13/4282 ,  G06F1/3293 ,  G06F2213/0016

    Abstract: Systems, methods, and apparatus are described that enable communication of in-band reset signals over a serial bus. A method performed at a slave device coupled to the serial bus includes configuring a reset controller to operate in one of plural modes, identifying a first reset pattern in signaling received from a multi-wire serial bus, complying with one or more transmissions defined by the protocol, asserting a reset input of a processing circuit in the slave device responsive to an identification of the first reset pattern when the reset controller is operated in a first mode, and ignoring the first reset pattern when the reset controller is operated in a second mode. The signaling received from the multi-wire serial bus may include one or more transmissions defined by a protocol used on the multi-wire serial bus. The reset controller may operate autonomously from the processing circuit in the first mode.

Patent Agency Ranking