公开(公告)号：US20150357018A1

公开(公告)日：2015-12-10

申请号：US14827771

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/222

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

Abstract translation: 公开了一种在存储器控制器中的操作方法。 该方法包括接收相对于在第一数据线上传播的第一数据具有第一相位关系的选通信号，以及相对于在第二数据线上传播的第二数据的第二相位关系。 基于第一相位关系产生第一采样信号，并且基于第二相位关系生成第二采样信号。 使用由第一采样信号计时的第一接收机接收第一数据信号。 使用由第二采样信号计时的第二接收机接收第二数据信号。

公开(公告)号：US09159388B2

公开(公告)日：2015-10-13

申请号：US14182389

申请日：2014-02-18

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: H04L7/00 ,  G11C7/22 ,  G06F1/10 ,  G11C7/10 ,  H03L7/07 ,  H03L7/081 ,  H04L7/033 ,  G11C7/04

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract translation: 存储器控制器从存储器件接收数据和相位提供信号。 相位提供信号不是时钟信号，而是被存储器控制器用来将本地数据采样信号与输入数据进行相位调整。 存储器控制器用数据采样信号对数据信号进行采样。 存储器控制器可以执行维护操作以更新相位提供和数据采样信号之间的相位关系。

公开(公告)号：US20150228340A1

公开(公告)日：2015-08-13

申请号：US14697182

申请日：2015-04-27

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C14/00

CPC classification number: G11C14/0018 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694

Abstract: A method of controlling a memory device is disclosed. The method includes receiving an address value that indicates a range of addresses within the memory device, each address within the range of addresses corresponding to storage locations within each of two distinct storage dice within the memory device. The address value is stored within a programmable register within the memory device.

Abstract translation: 公开了一种控制存储器件的方法。 该方法包括接收指示存储器设备内的地址范围的地址值，与存储器件内的两个不同存储裸片内的存储位置对应的地址范围内的每个地址。 地址值存储在存储器件内的可编程寄存器内。

公开(公告)号：US20150131388A1

公开(公告)日：2015-05-14

申请号：US14538524

申请日：2014-11-11

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G11C11/4093 ,  G11C5/04

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20130044552A1

公开(公告)日：2013-02-21

申请号：US13656238

申请日：2012-10-19

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C8/18

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/222

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

公开(公告)号：US20250087261A1

公开(公告)日：2025-03-13

申请号：US18904454

申请日：2024-10-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20240095134A1

公开(公告)日：2024-03-21

申请号：US18373219

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/20 ,  G11C11/4093 ,  G11C29/52

CPC classification number: G06F11/2094 ,  G11C11/4093 ,  G11C29/52 ,  G06F2201/82

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US20240020249A1

公开(公告)日：2024-01-18

申请号：US18365696

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Craig E. Hampel ,  Scott C. Best ,  John Yan

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/1673 ,  G06F13/1694

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

公开(公告)号：US20230274775A1

公开(公告)日：2023-08-31

申请号：US18094895

申请日：2023-01-09

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C11/4076 ,  G06F13/16 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/222 ,  G11C7/04

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

公开(公告)号：US20230251794A1

公开(公告)日：2023-08-10

申请号：US18093258

申请日：2023-01-04

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0656 ,  G11C7/1006 ,  G06F3/0626 ,  G06F3/0673 ,  G11C5/04

Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.