公开(公告)号：US20190355751A1

公开(公告)日：2019-11-21

申请号：US16423884

申请日：2019-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd

Inventor： Yutaka OKAZAKI ,  Tomoaki Moriwaka ,  Shinya SASAGAWA ,  Takashi OHTSUKI

IPC: H01L27/12 ,  H01L21/768 ,  H01L29/786 ,  H01L29/66

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

公开(公告)号：US20190189643A1

公开(公告)日：2019-06-20

申请号：US16280792

申请日：2019-02-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota HODO ,  Motomu KURATA ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L21/463 ,  H01L21/467 ,  H01L21/768 ,  H01L29/786 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/1225 ,  H01L21/02565 ,  H01L21/463 ,  H01L21/467 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

公开(公告)号：US20180076332A1

公开(公告)日：2018-03-15

申请号：US15814925

申请日：2017-11-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Motomu KURATA ,  Yuta ENDO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/8258 ,  H01L22/12 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.

公开(公告)号：US20180013004A1

公开(公告)日：2018-01-11

申请号：US15696231

申请日：2017-09-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Takashi HAMADA ,  Akihisa SHIMOMURA ,  Satoru OKAMOTO ,  Katsuaki TOCHIBAYASHI

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12 ,  H01L21/4763 ,  H01L21/4757 ,  H01L29/66 ,  H01L21/465

CPC classification number: H01L29/7869 ,  H01L21/465 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

公开(公告)号：US20170229563A1

公开(公告)日：2017-08-10

申请号：US15498782

申请日：2017-04-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/66 ,  H01L27/12

CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

公开(公告)号：US20170154789A1

公开(公告)日：2017-06-01

申请号：US15429547

申请日：2017-02-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Katsuaki TOCHIBAYASHI

IPC: H01L21/44 ,  H01L29/66 ,  H01L27/12 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L21/4757

CPC classification number: H01L21/44 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/47573 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/401 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device using an oxide semiconductor. The semiconductor device includes a first electrode layer; a second electrode layer positioned over the first electrode layer and including a stacked-layer structure of a first conductive layer and a second conductive layer; and an oxide semiconductor film and an insulating film positioned between the first electrode layer and the second electrode layer in a thickness direction. The first conductive layer and the insulating film have a first opening portion in a region overlapping with the first electrode layer, The oxide semiconductor film has a second opening portion in a region overlapping with the first opening portion. The second conductive layer is in contact with the first electrode layer exposed in the first opening portion and the second opening portion.

公开(公告)号：US20170117299A1

公开(公告)日：2017-04-27

申请号：US15386017

申请日：2016-12-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Ryota HODO ,  Katsuaki TOCHIBAYASHI ,  Tomoaki MORIWAKA ,  Jiro NISHIDA ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L27/13 ,  H01L21/84 ,  H01L23/522

Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.

公开(公告)号：US20160372606A1

公开(公告)日：2016-12-22

申请号：US15182812

申请日：2016-06-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke MATSUBAYASHI ,  Masaharu NAGAI ,  Yoshiaki YAMAMOTO ,  Takashi HAMADA ,  Yutaka OKAZAKI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Naoto YAMADE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/425 ,  H01L21/46 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

Abstract translation: 一种半导体器件包括：衬底上的第一绝缘层，第一绝缘层上的第一金属氧化物层，第一金属氧化物层上的氧化物半导体层，氧化物半导体层上的第二金属氧化物层， 第二金属氧化物层，第二金属氧化物层上的第二绝缘层，以及栅极绝缘层上的栅电极层。 栅极绝缘层包括与栅电极层的侧表面接触的区域。 第二绝缘层包括与栅极绝缘层接触的区域。 氧化物半导体层包括第一至第三区域。 第一区域包括与栅电极层重叠的区域。 位于第一和第三区域之间的第二区域包括与栅极绝缘层或第二绝缘层重叠的区域。 第二和第三区域各自包括含有元素N（N是磷，氩或氙）的区域。

公开(公告)号：US20160359050A1

公开(公告)日：2016-12-08

申请号：US15244019

申请日：2016-08-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78696

Abstract: When an oxide semiconductor film is microfabricated, with the use of a hard mask, unevenness of a side surface of the oxide semiconductor film can be suppressed. Specifically, a semiconductor device comprises an oxide semiconductor film over an insulating surface; a first hard mask and a second hard mask over the oxide semiconductor film; a source electrode over the oxide semiconductor film and the first hard mask; a drain electrode over the oxide semiconductor film and the second hard mask; a gate insulating film over the source electrode and the drain electrode; and a gate electrode overlapping with the gate insulating film and the oxide semiconductor film, and the first and second hard masks have conductivity.

Abstract translation: 当氧化物半导体膜被微细加工时，通过使用硬掩模，可以抑制氧化物半导体膜的侧表面的不均匀性。 具体地，半导体器件包括绝缘表面上的氧化物半导体膜; 氧化物半导体膜上的第一硬掩模和第二硬掩模; 所述氧化物半导体膜上的源电极和所述第一硬掩模; 所述氧化物半导体膜和所述第二硬掩模上的漏电极; 源电极和漏电极上的栅极绝缘膜; 以及与栅极绝缘膜和氧化物半导体膜重叠的栅电极，并且第一和第二硬掩模具有导电性。

公开(公告)号：US20160343587A1

公开(公告)日：2016-11-24

申请号：US15226003

申请日：2016-08-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Fumika TAGUCHI ,  Yoshinori IEDA

IPC: H01L21/3213 ,  H01L21/48 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L27/1288 ,  H01L21/31053 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/486 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124

Abstract: It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield. In a wiring board or a semiconductor device having a multilayer wiring structure, a conductive layer having a curved surface is used in connection between conductive layers used for the wirings. The top of a conductive layer in a lower layer exposed by removal of an insulating layer therearound has a curved surface, so that coverage of the conductive layer in the lower layer with a conductive layer in an upper layer stacked thereover can be favorable. A conductive layer is etched using a resist mask having a curved surface, so that a conductive layer having a curved surface is formed.

Abstract translation: 本发明的目的是减少集成度增加的布线板或半导体器件的导通不良。 另一个目的是以高产率制造高度可靠的布线板或半导体器件。 在具有多层布线结构的布线板或半导体器件中，具有弯曲表面的导电层用于连接用于布线的导电层。 通过去除其周围的绝缘层而暴露的下层中的导电层的顶部具有弯曲表面，使得下层中的导电层与其上层叠的上层中的导电层的覆盖率可能是有利的。 使用具有弯曲表面的抗蚀剂掩模蚀刻导电层，从而形成具有弯曲表面的导电层。