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公开(公告)号：US06771374B1
公开(公告)日：2004-08-03
申请号：US10050758
申请日：2002-01-16
IPC分类号： G01N2155
CPC分类号： G01N21/211 , G01B11/0675 , G01N21/4738 , G01N21/9501 , Y10T428/21
摘要： A system and method are disclosed for monitoring characteristics of a rotating substrate. As the substrate rotates in an environment, an incident light beam is emitted onto the substrate near an axis about which the substrate rotates. The emission of the incident beam is controlled as a function of the angular orientation of the substrate, so that the incident beam selectively interrogates a central region of the substrate to facilitate measuring and/or inspecting characteristics of the substrate.
摘要翻译： 公开了一种用于监测旋转衬底的特性的系统和方法。 当衬底在环境中旋转时，入射光束在衬底旋转的轴附近被发射到衬底上。 入射光束的发射被控制为衬底的角度取向的函数，使得入射光束选择性地询问衬底的中心区域以便于测量和/或检查衬底的特性。
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公开(公告)号：US06727995B1
公开(公告)日：2004-04-27
申请号：US09903884
申请日：2001-07-12
IPC分类号： G01B1106
CPC分类号： H01L21/28194 , G01B11/0625 , H01L21/67253 , H01L29/517 , H01L29/518
摘要： A system for regulating gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more gate oxide layers being deposited and/or formed on a wafer. Light reflected from the gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective gate oxide layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective gate oxide layers on the wafer. The system also includes a plurality of gate oxide layer formers where each gate oxide former corresponds to a respective portion of the wafer and provides for gate oxide layer formation thereon. The processor selectively controls the gate oxide layer formers to regulate gate oxide layer formation on the respective gate oxide layer formations on the wafer.
摘要翻译： 提供了一种用于调节栅氧化层形成的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个栅极氧化物层。 从栅极氧化层反射的光被测量系统收集，该系统处理所收集的光。 所收集的光表示晶片上各个栅极氧化物层的厚度和/或均匀性。 测量系统向处理器提供厚度和/或均匀性相关数据，其确定晶片上各个栅极氧化物层的厚度和/或均匀性。 该系统还包括多个栅极氧化物层形成器，其中每个栅极氧化物形成体对应于晶片的相应部分并且在其上形成栅极氧化物层。 处理器选择性地控制栅极氧化物层形成器以调节在晶片上的各个栅极氧化物层形成上的栅极氧化物层形成。
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143.发明授权公开(公告)号：US06664030B1
公开(公告)日：2003-12-16
申请号：US09779981
申请日：2001-02-09
IPC分类号： C23C804
摘要： An exemplary method of constructing an alternating phase-shifting mask is described. This method can include providing a vapor in a vapor chamber containing a mask blank, and applying a laser to selected areas of the mask blank to deposit material on the integrated circuit substrate. The material is configured to cause a 180° phase shift at the wavelengths the mask is designed for such as 248 nm, 193 nm or 157 nm.
摘要翻译： 描述构成交替移相掩模的示例性方法。 该方法可以包括在包含掩模坯料的蒸气室中提供蒸气，以及将激光施加到掩模坯料的选定区域以将材料沉积在集成电路基板上。 该材料被配置为在掩模设计为例如248nm，193nm或157nm的波长处引起180°相移。
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公开(公告)号：US06649426B2
公开(公告)日：2003-11-18
申请号：US09893824
申请日：2001-06-28
IPC分类号： G01R3126
摘要： The present invention relates to systems and methods to regulate spacer deposition. The present invention employs a spacer deposition controller to control a spacer deposition component that deposits a spacer on a portion of a wafer. During and/or after spacer deposition, light can be directed at the spacer, wherein light reflected from the spacer is measured to determine parameters associated with the spacer deposition process. A processor operatively coupled to a measurement system and the spacer deposition controller utilizes the parameters to determine if the spacer process is proceeding in a suitable manner via comparing the measured parameters with stored acceptable parameters. If it is determined that the spacer deposition process is not proceeding as desired, then the measured parameters can be employed by the spacer deposition controller to adjust the spacer deposition process on the portion of the wafer and on subsequent portions of wafers.
摘要翻译： 本发明涉及调节间隔物沉积的系统和方法。 本发明使用间隔物沉积控制器来控制将间隔物沉积在晶片的一部分上的间隔物沉积组分。 在间隔物沉积期间和/或之后，可以将光引向间隔物，其中测量从间隔物反射的光以确定与间隔物沉积过程相关的参数。 可操作地耦合到测量系统的处理器和间隔物沉积控制器利用参数来确定间隔物过程是否以适当的方式通过将测量的参数与存储的可接受参数进行比较来进行。 如果确定间隔物沉积过程没有按需要进行，则可以通过间隔物沉积控制器来采用测量的参数来调整晶片部分和晶片的后续部分上的间隔物沉积过程。
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145.发明授权公开(公告)号：US06627526B1
公开(公告)日：2003-09-30
申请号：US09805287
申请日：2001-03-13
申请人： Wenge Yang , Bhanwar Singh
发明人： Wenge Yang , Bhanwar Singh
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/0331 , H01L21/28052 , H01L21/32051
摘要： A process for making semiconductor structures, and the resulting highly conductive semiconductor structures, includes using damascene process to form a structure with a thin adhesive layer and overlaying conductive layer. The highly conductive semiconductor structure has a thickness less than about 3000 Å, preferably less than about 2600 Å, and incorporates an adhesive layer that is preferably less than about 100 Å thick. Despite the reduced profile and topography of the structure, it is more conductive than prior structures, and provides a robust device.
摘要翻译： 制造半导体结构的方法以及所得到的高导电半导体结构包括使用镶嵌工艺来形成具有薄的粘合层和覆盖导电层的结构。 高度导电的半导体结构具有小于约3000埃，优选小于约2600埃的厚度，并且包含优选小于约100埃的粘合剂层。 尽管结构的轮廓和形貌减小，但它比现有结构更具导电性，并且提供了一种坚固的装置。
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公开(公告)号：US06605546B1
公开(公告)日：2003-08-12
申请号：US09901699
申请日：2001-07-11
IPC分类号： H01L21302
CPC分类号： H01L21/76808
摘要： A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.
摘要翻译： 一种用于形成半导体器件的方法包括在半导体衬底上形成第一层。 通过第一层形成至少一个孔。 在至少一个孔中形成底部抗反射涂层（BARC）层。 执行第一次加热以将BARC层加热至流动温度。 执行第二次加热以将BARC层加热至硬化温度，使得BARC层硬化，其中硬化温度大于流动温度。 进行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的硬化的BARC层在蚀刻期间用作耐蚀刻层。 作为第二加热步骤的替代方案，BARC可以简单地硬化。 第一和第二加热可以在加热室内进行，而不去除半导体衬底。
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147.发明授权Oxide/nitride or oxide/nitride/oxide thickness measurement using scatterometry 失效使用散射测量的氧化物/氮化物或氧化物/氮化物/氧化物厚度测量公开(公告)号：US06589804B1
公开(公告)日：2003-07-08
申请号：US09904089
申请日：2001-07-12
IPC分类号： H01L2100
CPC分类号： G01B11/0625
摘要： A system for regulating ON and/or ONO dielectric formation is provided. The system includes one or more light sources, each light source directing light to one or more oxide and/or nitride layers being deposited and/or formed on a wafer. Light reflected from the oxide and/or nitride layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The system also includes a plurality of oxide/nitride formers; each oxide/nitride former corresponding to a respective portion of the wafer and providing for ON and/or ONO formation thereon. The processor selectively controls the oxide/nitride formers to regulate oxide and/or nitride layer formation on the respective ON and/or ONO formations on the wafer.
摘要翻译： 提供了一种用于调节ON和/或ONO电介质形成的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个氧化物和/或氮化物层。 从氧化物和/或氮化物层反射的光被测量系统收集，该系统处理收集的光。 所收集的光指示晶片上各个氧化物和/或氮化物层的厚度和/或均匀性。 测量系统向处理器提供厚度和/或均匀性相关数据，其确定晶片上相应氧化物和/或氮化物层的厚度和/或均匀性。 该系统还包括多个氧化物/氮化物成形器; 每个氧化物/氮化物成形器对应于晶片的相应部分并且在其上提供ON和/或ONO形成。 处理器选择性地控制氧化物/氮化物成形器以调节晶片上相应的ON和/或ONO形成上的氧化物和/或氮化物层的形成。
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公开(公告)号：US06562248B1
公开(公告)日：2003-05-13
申请号：US09817518
申请日：2001-03-26
IPC分类号： G01N2100
摘要： A system for monitoring and controlling aperture etching in a complimentary phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. Light passing through the apertures may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the depth and/or width of the openings on the mask. The measuring system provides depth and/or width related data to a processor that determines the acceptability of the aperture depth and/or width. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor selectively controls the etching devices so as to regulate aperture etching.
摘要翻译： 提供了一种用于在补偿相移掩模中监测和控制孔蚀刻的系统。 该系统包括一个或多个光源，每个光源将光引导到在掩模上蚀刻的一个或多个孔。 从孔径反射的光由测量系统收集，该系统处理所收集的光。 通过孔的光可以类似地由处理收集的光的测量系统收集。 收集的光指示掩模上的开口的深度和/或宽度。 测量系统向确定孔径深度和/或宽度的可接受性的处理器提供深度和/或宽度相关数据。 该系统还包括与掩模中的孔蚀刻相关联的多个蚀刻装置。 处理器选择性地控制蚀刻装置以调节孔径蚀刻。
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149.发明授权Wafer based temperature sensors for characterizing chemical mechanical polishing processes 有权用于表征化学机械抛光工艺的基于晶圆的温度传感器公开(公告)号：US06562185B2
公开(公告)日：2003-05-13
申请号：US09955552
申请日：2001-09-18
IPC分类号： B24B3700
CPC分类号： B24B37/015
摘要： A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties. Such characterization can be employed, for example, to better understand a CMP process, to facilitate initializing subsequent chemical mechanical polishing processes and/or apparatus and/or to control such chemical mechanical polishing processes and/or apparatus by monitoring and/or controlling wafer temperature.
摘要翻译： 提供了表征化学机械抛光工艺的系统。 该系统包括具有位于金属，多晶硅和/或电介质层和/或衬底中和/或上的金属，多晶硅和/或电介质层和/或衬底和温度传感器的晶片。 该系统还包括一个温度监控系统，可以从温度传感器读取晶圆温度，并且可以分析晶圆温度以表征化学机械抛光过程。 这种表征包括产生关于晶片温度和抛光速率之间的关系的信息，抛光均匀性和在抛光期间引入缺陷。 这些关系与晶片温度相关，如与抛光时间，压力，速度，浆料性质和晶片/金属层性质等参数相关。 可以采用这种表征，例如，更好地理解CMP工艺，以便于初始化随后的化学机械抛光工艺和/或设备和/或通过监测和/或控制晶片温度来控制这种化学机械抛光工艺和/或设备 。
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150.发明授权Use of silicon containing imaging layer to define sub-resolution gate structures 有权使用含硅成像层来定义次分辨率门结构公开(公告)号：US06534418B1
公开(公告)日：2003-03-18
申请号：US09845656
申请日：2001-04-30
IPC分类号： H01L21302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/28123 , H01L29/6659 , H01L29/7833
摘要： An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
摘要翻译： 使用含硅成像层来限定次分辨率门结构的示例性方法可以包括在多晶硅层上沉积抗反射涂层，在抗反射涂层上沉积成像层，选择性地蚀刻抗反射涂层以形成 使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。 因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用修剪蚀刻技术，而不会有抗蚀剂侵蚀或高宽比图案崩溃的风险。 这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。
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