公开(公告)号：US08242479B2

公开(公告)日：2012-08-14

申请号：US12742841

申请日：2008-11-14

Applicant: Yoshio Kawashima ,  Takumi Mikawa ,  Ryoko Miyanaga ,  Takeshi Takagi

Inventor： Yoshio Kawashima ,  Takumi Mikawa ,  Ryoko Miyanaga ,  Takeshi Takagi

IPC: H01L29/02

CPC classification number: H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

Abstract: A nonvolatile memory device includes via holes (12) formed at cross sections where first wires (11) cross second wires (14), respectively, and current control elements (13) each including a current control layer (13b), a first electrode layer (13a) and a second electrode layer (13c) such that the current control layer (13b) is sandwiched between the first electrode layer (13a) and the second electrode layer (13c), in which resistance variable elements (15) are provided inside the via holes (12), respectively, the first electrode layer (13a) is disposed so as to cover the via hole (12), the current control layer (13b) is disposed so as to cover the first electrode layer (13a), the second electrode layer (13c) is disposed on the current control layer (13b), a wire layer (14a) of the second wire is disposed on the second electrode layer (13c), and the second wires (14) each includes the current control layer (13b), the second electrode layer (13c) and the wire layer (14a) of the second wire.

Abstract translation: 非易失性存储器件包括分别形成在第一布线（11）与第二布线（14）交叉的横截面处的通孔（12），以及各自包括电流控制层（13b）的电流控制元件（13），第一电极层 （13a）和第二电极层（13c），使得电流控制层（13b）夹在第一电极层（13a）和第二电极层（13c）之间，其中电阻可变元件（15）设置在其内 通孔（12）分别设置成覆盖通孔（12），电流控制层（13b）被设置成覆盖第一电极层（13a）， 第二电极层（13c）设置在电流控制层（13b）上，第二导线的导线层（14a）设置在第二电极层（13c）上，第二导线（14）各自包括电流 控制层（13b），第二电极层（13c）和第二wi的导线层（14a） 回覆。

公开(公告)号：US08125818B2

公开(公告)日：2012-02-28

申请号：US12918874

申请日：2009-02-25

Applicant: Shunsaku Muraoka ,  Takeshi Takagi ,  Kazuhiko Shimakawa

Inventor： Shunsaku Muraoka ,  Takeshi Takagi ,  Kazuhiko Shimakawa

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/009 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: A method of programming a variable resistance element to be operated with stability and at a high speed is provided. The method programs a nonvolatile variable resistance element (10) including a variable resistance layer (3), which changes between a high resistance state and a low resistance state depending on a polarity of an applied electric pulse, and a lower electrode (2) and an upper electrode (4). The method includes: writing steps (S11) and (S15) to cause the variable resistance layer (3) to change from the low resistance state to the high resistance state by applying a write voltage pulse; and an erasing step (S13) to cause the variable resistance layer (3) to change from the high resistance state to the low resistance state. In the writing steps, a write voltage pulse is applied between the electrodes so as to satisfy |Vw1|>|Vw| where Vw1 represents a voltage value of the write voltage pulse in the first writing step (S11) after manufacturing the variable resistance element (10) and Vw represents a voltage value of the write voltage pulse in writing steps after the first writing step (S15) after manufacturing the variable resistance element (10).

Abstract translation: 提供了一种以稳定且高速度操作的可变电阻元件的编程方法。 该方法编程包括可变电阻层（3）的非易失性可变电阻元件（10），其根据所施加的电脉冲的极性在高电阻状态和低电阻状态之间变化;以及下电极（2）和 上电极（4）。 该方法包括：写入步骤（S11）和（S15），通过施加写入电压脉冲使可变电阻层（3）从低电阻状态变为高电阻状态; 以及使可变电阻层（3）从高电阻状态变为低电阻状态的擦除步骤（S13）。 在写入步骤中，在电极之间施加写入电压脉冲，以满足| Vw1 |> | Vw | 其中Vw1表示制造可变电阻元件（10）之后的第一写入步骤（S11）中的写入电压脉冲的电压值，Vw表示在第一写入步骤之后的写入步骤中的写入电压脉冲的电压值（S15） 在制造可变电阻元件（10）之后。

公开(公告)号：US20110185797A1

公开(公告)日：2011-08-04

申请号：US13122059

申请日：2009-10-02

Applicant: Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi

Inventor： Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi

IPC: G01N30/16 ,  G01N33/00

CPC classification number: G01N30/20 ,  G01N30/18 ,  G01N30/8658 ,  G01N30/8665 ,  G01N2030/042 ,  G01N2030/201 ,  G01N2030/202 ,  G01N2030/207

Abstract: An analyzing device includes a feeder connected to a container in which a sample is contained for sucking the sample from the container and feeding the sample, and a controller for performing control for feeding from the feeder to a measurer. In measuring the sample, the controller performs control so that results of a plurality of times of measurement are obtained with respect to the single container in which the sample is contained, without changing the container. This arrangement allows quick accuracy check.

Abstract translation: 分析装置包括连接到容器的进料器，在该容器中容纳样品以从容器吸取样品并进料样品;以及控制器，用于进行从进料器进给到测量器的控制。 在测量样品时，控制器执行控制，使得相对于容纳样品的单个容器获得多次测量的结果，而不改变容器。 这种安排允许快速准确的检查。

公开(公告)号：US20110103132A1

公开(公告)日：2011-05-05

申请号：US13000243

申请日：2010-04-22

Applicant: Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

Inventor： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

Abstract: Provided are a nonvolatile memory element which is capable of effectively preventing an event that when a failure occurs in a certain nonvolatile memory element, data cannot be written to and read from another nonvolatile memory element belonging to the same column or row as that to which the nonvolatile memory element in a failed state belongs, and a semiconductor memory device including the nonvolatile memory element.A nonvolatile memory element comprises a current controlling element (112) having a non-linear current-voltage characteristic, a resistance variable element (105) which changes reversibly between a low-resistance state and a high-resistance state in which a resistance value of the resistance variable element is higher than a resistance value of the resistance variable element in the low-resistance state, in response to voltage pulses applied, and a fuse (103), the current controlling element (112), the resistance variable element (105) and the fuse (103) being connected in series, and the fuse (103) being configured to be blown when the current controlling element (112) is substantially short-circuited.

Abstract translation: 提供了一种非易失性存储元件，其能够有效地防止当在某个非易失性存储元件中发生故障时的事件，不能将数据写入和读取与属于同一列或列的另一非易失性存储器元件 处于故障状态的非易失性存储元件属于非易失性存储元件，以及包括非易失性存储元件的半导体存储器件。 非易失性存储元件包括具有非线性电流 - 电压特性的电流控制元件（112），在低电阻状态和高电阻状态之间可逆地改变的电阻可变元件（105），其中电阻值 电阻可变元件响应于施加的电压脉冲而高于低电阻状态下的电阻可变元件的电阻值，以及熔丝（103），电流控制元件（112），电阻可变元件（105） ）和保险丝（103）串联连接，并且熔断器（103）被配置为当电流控制元件（112）基本上短路时被断开。

公开(公告)号：US20110103131A1

公开(公告)日：2011-05-05

申请号：US12994910

申请日：2010-04-23

Applicant: Koji Katayama ,  Takeshi Takagi

Inventor： Koji Katayama ,  Takeshi Takagi

IPC: G11C11/00 ,  H01L45/00

CPC classification number: G11C13/003 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1683

Abstract: Provided is a nonvolatile memory element which has a small variation in operation and allow stable operation. The nonvolatile memory element includes: a first electrode (102); a second electrode (106); a variable resistance layer (105) which is formed between the electrodes (102 and 106) and is connected to the electrodes (102 and 106), and which reversibly changes between a high resistance state and a low resistance state according to a polarity of a voltage applied between the electrodes (102 and 106); and a fixed resistance layer (104) which has a resistance value that is 0.1 and 10 times as large as a resistance value of the variable resistance layer in the high resistance state, the fixed resistance layer (104) being formed between the electrodes (102 and 106) and being electrically connected to at least a part of the variable resistance layer (105).

Abstract translation: 提供了一种非易失性存储元件，其具有小的操作变化并且允许稳定的操​​作。 非易失性存储元件包括：第一电极（102）; 第二电极（106）; 形成在所述电极（102和106）之间并连接到所述电极（102和106）的可变电阻层（105），并且根据所述电极（102和106）的极性在高电阻状态和低电阻状态之间可逆地变化 施加在电极（102和106）之间的电压; 和固定电阻层（104），其电阻值是高电阻状态下的可变电阻层的电阻值的0.1和10倍，固定电阻层（104）形成在电极（102）之间 和106），并且电连接到可变电阻层（105）的至少一部分。

公开(公告)号：US20110080770A1

公开(公告)日：2011-04-07

申请号：US12994462

申请日：2010-03-25

Applicant: Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

Inventor： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

IPC: G11C11/21

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: Applying a writing voltage pulse having a first polarity to a metal oxide layer (3) to change a resistance state of the metal oxide layer (3) from high to low so as to render the resistance state a write state, applying an erasing voltage pulse having a second polarity different from the first polarity to the metal oxide layer (3) to change the resistance state of the metal oxide layer (3) from low to high so as to render the resistance state an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer (3) before the applying of a writing voltage pulse is performed for a first time, to change a resistance value of an initial state of the metal oxide layer (3) are included, and R0>RH>RL and |V0|>|Ve|≧|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer (3), and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.

Abstract translation: 将具有第一极性的写入电压脉冲施加到金属氧化物层（3）以将金属氧化物层（3）的电阻状态从高变为低，以使电阻状态成为写入状态，施加擦除电压脉冲 具有与第一极性不同于金属氧化物层（3）的第二极性，以将金属氧化物层（3）的电阻状态从低到高改变为使得电阻状态为擦除状态，并且施加初始电压 首先执行施加写入电压脉冲之前对金属氧化物层（3）具有第二极性的脉冲，以改变金属氧化物层（3）的初始状态的电阻值，并且R0 > RH> RL，| V0 |> | Ve |≥| Vw | 满足R0，RL和RH分别为金属氧化物层（3）的初始，写入和擦除状态的电阻值，V0，Vw和Ve为初始，写入和写入的电压值， 并分别擦除电压脉冲。

公开(公告)号：US20110051500A1

公开(公告)日：2011-03-03

申请号：US12990323

申请日：2009-12-04

Applicant: Takeshi Takagi ,  Zhiqiang Wei ,  Takeki Ninomiya ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa

Inventor： Takeshi Takagi ,  Zhiqiang Wei ,  Takeki Ninomiya ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa

IPC: G11C11/21 ,  G11C11/36 ,  G11C11/40

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: Provided is a nonvolatile memory element which is capable of performing a stable resistance change operation at a low breakdown voltage.A nonvolatile memory element (100) includes: a first electrode layer (103); a second electrode layer (105); and a variable resistance layer (104) which is placed between the electrodes (103 and 105), and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between the electrodes (103 and 105). The variable resistance layer (104) is formed by stacking a first oxide layer (104a) including an oxide of a first transition metal and a second oxide layer (104b) including an oxide of a second transition metal which is different from the first transition metal. At least one of the following conditions is satisfied: (1) a dielectric constant of the second oxide layer (104b) is larger than a dielectric constant of the first oxide layer (104a); and (2) a band gap of the second oxide layer (104b) is smaller than a band gap of the first oxide layer (104a).

Abstract translation: 提供一种能够在低击穿电压下进行稳定的电阻变化操作的非易失性存储元件。 非易失性存储元件（100）包括：第一电极层（103）; 第二电极层（105）; 和位于电极（103和105）之间的可变电阻层（104），并且其电阻状态基于在电极（103和103）之间施加的电压的极性而在高电阻状态和低电阻状态之间可逆地变化 105）。 可变电阻层（104）通过堆叠包括第一过渡金属的氧化物的第一氧化物层（104a）和包含与第一过渡金属不同的第二过渡金属的氧化物的第二氧化物层（104b） 。 满足以下条件中的至少一个：（1）第二氧化物层（104b）的介电常数大于第一氧化物层（104a）的介电常数; 和（2）第二氧化物层（104b）的带隙小于第一氧化物层（104a）的带隙。

公开(公告)号：US20110044088A1

公开(公告)日：2011-02-24

申请号：US12743472

申请日：2009-08-20

Applicant: Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Satoru Mitani ,  Koji Katayama ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Takeshi Takagi

Inventor： Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Satoru Mitani ,  Koji Katayama ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Takeshi Takagi

IPC: G11C11/34 ,  H01L27/105 ,  H01L21/02

CPC classification number: H01L45/147 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOx and MOy (where x

Abstract translation: 一种可变电阻非易失性存储装置，包括：（i）半导体衬底（301），（ii）具有下电极和上电极（309a，309c）的可变电阻元件（309） 和可变电阻层（309b），其电阻值基于各自具有不同极性的电压信号而被可逆地变化并施加在电极（309a，309c）之间，以及（iii）形成在基板上的MOS晶体管 （301），其中所述可变电阻层（309b）包括：具有组成MOx和MOy（其中x

公开(公告)号：US07884346B2

公开(公告)日：2011-02-08

申请号：US12295500

申请日：2007-03-27

Applicant: Takumi Mikawa ,  Takeshi Takagi

Inventor： Takumi Mikawa ,  Takeshi Takagi

IPC: H01L47/00 ,  G11C11/00

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1691

Abstract: A nonvolatile memory element comprising: a first electrode 2; a second electrode 6 formed above the first electrode 2; a variable resistance film 4 formed between the first electrode 2 and the second electrode 6, a resistance value of the variable resistance film 4 being increased or decreased by an electric pulse applied between the first and second electrodes 2, 6; and an interlayer dielectric film 3 provided between the first and second electrodes 2, 6, wherein the interlayer dielectric film 3 is provided with an opening extending from a surface thereof to the first electrode 2; the variable resistance film 4 is formed at an inner wall face of the opening; and an interior region of the opening which is defined by the variable resistance film 4 is filled with an embedded insulating film 5.

Abstract translation: 一种非易失性存储元件，包括：第一电极2; 形成在第一电极2上方的第二电极6; 形成在第一电极2和第二电极6之间的可变电阻膜4，通过施加在第一和第二电极2,6之间的电脉冲，可变电阻膜4的电阻值增加或减小; 以及设置在第一和第二电极2,6之间的层间绝缘膜3，其中层间绝缘膜3设置有从其表面延伸到第一电极2的开口; 可变电阻膜4形成在开口的内壁面上; 并且由可变电阻膜4限定的开口的内部区域填充有嵌入绝缘膜5。

公开(公告)号：US20100299072A1

公开(公告)日：2010-11-25

申请号：US12451085

申请日：2008-04-25

Applicant: Tatsuo Kamata ,  Takeshi Takagi ,  Yuki Ito

Inventor： Tatsuo Kamata ,  Takeshi Takagi ,  Yuki Ito

IPC: G06F19/00 ,  G01N33/50

CPC classification number: G01N27/3274 ,  G01N30/8606 ,  G01N33/5438 ,  G01N33/721 ,  G01N33/96 ,  G01N2030/146 ,  G01N2030/8411 ,  G01N2030/8822

Abstract: This invention is a method for a substrate concentration measurement method including measuring a concentration of a substrate in a blood specimen containing hemoglobin. In the method, the substrate concentration is calculated by using a measurement value correlating with a substrate concentration influenced by hemoglobin, and a hemoglobin concentration or a value correlating with the hemoglobin concentration. A substrate concentration is calculated by correcting the measurement value Re correlating with the substrate concentration based on the following Formulae 1 and 2: [Formula 1] Corrected value=100×Re/V (%), wherein V (%) represents a value with respect to plasma (a ratio of a measurement value influenced by hemoglobin with respect to a measurement value obtained by measuring plasma), and Re represents the measurement value correlating with the substrate concentration influenced by hemoglobin; [Formula 2] Value with respect to plasma V (%)=(Vmax×Re)/(Km+Re)+B, wherein Vmax represents a value obtained by subtracting an intercept (B) from the value (V) with respect to plasma which is maintained constant even when the measurement value influenced by hemoglobin increases, Km represents a value of Re at which the value V (%) with respect to plasma becomes Vmax/2, and B represents a value (constant) of V (%) with respect to plasma when Re is 0.

Abstract translation: 本发明是一种测定含有血红蛋白的血液标本中的基质浓度的基板浓度测定方法。 在该方法中，通过使用与受血红蛋白影响的底物浓度相关的测定值和血红蛋白浓度或与血红蛋白浓度相关的值来计算底物浓度。 通过基于以下公式1和2校正与底物浓度相关的测量值Re来计算底物浓度：[式1]校正值= 100×Re / V（％），其中V（％）表示与 对血浆的影响（由血红蛋白影响的测定值相对于通过测定血浆得到的测定值的比例），Re表示与由血红蛋白影响的底物浓度相关的测定值; [式2]相对于等离子体V（％）=（Vmax×Re）/（Km + Re）+ B的值，其中Vmax表示通过从相对于（V）的值（V）减去截距（B） 即使当受血红蛋白影响的测量值增加时，也保持恒定的等离子体，Km表示相对于等离子体的值V（％）为Vmax / 2的Re值，B表示V（％）的值（常数） ）相对于等离子体。