-
141.发明申请公开(公告)号：US20210286400A1
公开(公告)日：2021-09-16
申请号：US17261358
申请日：2019-08-09
摘要： A semiconductor circuit apparatus of the present disclosure includes a control circuit controlling a clock signal externally input, a drive circuit performing a switching operation according to a pulse signal provided by the control circuit, a series connection circuit including an inductor element, a switch element, and a capacitive element connected in series between a signal line and a fixed potential node, the series connection circuit forming an LC resonance circuit, and a level detection circuit having an input end connected to the signal line. An output from the level detection circuit is fed back to the control circuit.
-
公开(公告)号：US20210273642A1
公开(公告)日：2021-09-02
申请号：US16822025
申请日：2020-03-18
发明人： Jen-Chu Wu , Po-Min Cheng , Wun-Jian Su , Chia-Hui Yu
摘要： A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.
-
公开(公告)号：US20210270899A1
公开(公告)日：2021-09-02
申请号：US17025511
申请日：2020-09-18
发明人： Wonhyun Choi , Hyunchul Hwang , Minsu Kim
IPC分类号： G01R31/3185 , G06F1/10 , G01R31/3177
摘要： High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.
-
公开(公告)号：US11100976B2
公开(公告)日：2021-08-24
申请号：US16897157
申请日：2020-06-09
申请人： Rambus Inc.
发明人： Frederick A. Ware
IPC分类号： G11C11/4076 , G11C7/22 , G11C7/10 , G06F1/10 , G11C11/409 , G06F13/16 , G06F13/42 , G11C8/18
摘要： An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.
-
公开(公告)号：US11099601B2
公开(公告)日：2021-08-24
申请号：US16556206
申请日：2019-08-29
发明人： Steven R. Carlough , Susan M. Eickhoff , Michael B. Spear , Gary A. Van Huben , Stephen D. Wyatt
摘要： A calibration controller determines a latest arriving data strobe from at least one data chip at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller determines whether external feedback of the at least one data chip is required. The calibration controller, in response to determining that external feedback of the at least one data chip is required, aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe by applying a 180 degree phase align of the chip clock through one or more latches, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary.
-
公开(公告)号：US11094363B2
公开(公告)日：2021-08-17
申请号：US16825759
申请日：2020-03-20
IPC分类号： G06F12/00 , G11C11/406 , G06F1/10 , G06F3/06 , G11C11/409
摘要： Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock. Specifically, at least one of each group of memory units counts pulses of a self-refresh clock and invokes a self-refresh after every nth pulse of a cycle of pulses while not invoking a self-refresh on all other pulses of the cycle of pulses.
-
公开(公告)号：US11092994B1
公开(公告)日：2021-08-17
申请号：US17034853
申请日：2020-09-28
申请人： SK hynix Inc.
发明人： Gi Moon Hong , Kyu Dong Hwang
摘要： A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.
-
公开(公告)号：US20210247834A1
公开(公告)日：2021-08-12
申请号：US17159318
申请日：2021-01-27
发明人： JAE GON LEE , AH CHAN KIM , JIN OOK SONG , JAE YOUNG LEE , YOUN SIK CHOI
IPC分类号： G06F1/3234 , G06F1/06 , G06F13/42 , H04J3/06 , H04J3/14 , H04L12/933 , G06F1/20 , G06F1/3237 , G06F1/10
摘要： A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.
-
公开(公告)号：US20210240218A1
公开(公告)日：2021-08-05
申请号：US17217822
申请日：2021-03-30
申请人： SigmaSense, LLC.
发明人： Richard Stuart Seger, JR. , Daniel Keith Van Ostrand , Gerald Dale Morrison , Timothy W. Markison
IPC分类号： G06F1/10 , H03M1/12 , H03K19/17784 , H04B1/00
摘要： A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert analog outbound data into an analog transmit signal and convert analog receive signals into analog inbound data, a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data, and a receive analog to digital circuit including an analog to digital converter, a digital filtering circuit, and a data formatting module. The data formatting module includes a sample and hold circuit operable to sample and hold an n-bit digital value of filtered digital data from the digital filtering circuit to produce an n-bit sampled digital data value, a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value, and a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.
-
公开(公告)号：US11073861B2
公开(公告)日：2021-07-27
申请号：US16962517
申请日：2018-03-06
发明人： Ignatius Bezzam , Neelam Rawat
摘要： Disclosed is a resonant circuit and method for matched clock and data timing performance for improving timing closure of digital circuits on advanced semiconductor manufacturing processes. The matched resonance circuit comprises pulse generator circuit (202) and plurality of generating latches (206A-N) and plurality of sampling latches (304A-N). The pulse generator circuit (202) comprises plurality of inverters (210A-N), optimum resistance (214) and exclusive OR (Ex-OR) gate (218) which are connected in series and a matched capacitance. The pulse generator circuit (202) generates timing pulse output using one or more buffers and clock inductor. Each generating latch receives clock timing pulse output as timing pulse into plurality of sampling flip-flop latches (304A-N) through clock sample path (CS) to match arrival of timing pulse and outputs of plurality of input data lines that are resonated by connecting one or more of respective load capacitances with at least one shared inductor (208).
-
-
-
-
-
-
-
-
-
搜索结果
3192 条记录 (耗时 0.033 秒)
