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    Circuitry for high-bandwidth, low-latency machine learning
    153.
    发明授权
    Circuitry for high-bandwidth, low-latency machine learning 有权

    公开(公告)号：US11899746B2

    公开(公告)日：2024-02-13

    申请号：US17560950

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Martin Langhammer ,  Andrei-Mihai Hagiescu-Miriste

    IPC: G06F17/16 ,  G06N5/00 ,  G06N3/063

    CPC classification number: G06F17/16 ,  G06N5/00 ,  G06N3/063

    Abstract: The present disclosure relates generally to techniques for efficiently performing operations associated with artificial intelligence (AI), machine learning (ML), and/or deep learning (DL) applications, such as training and/or interference calculations, using an integrated circuit device. More specifically, the present disclosure relates to an integrated circuit design implemented to perform these operations with low latency and/or a high bandwidth of data. For example, embodiments of a computationally dense digital signal processing (DSP) circuitry, implemented to efficiently perform one or more arithmetic operations (e.g., a dot-product) on an input are disclosed. Moreover, embodiments described herein may relate to layout, design, and data scheduling of a processing element array implemented to compute matrix multiplications (e.g., systolic array multiplication).

    System for testing electrical connections between components
    155.
    发明授权
    System for testing electrical connections between components 有权

    公开(公告)号：US11899077B2

    公开(公告)日：2024-02-13

    申请号：US17226440

    申请日：2021-04-09

    Applicant: Schweitzer Engineering Laboratories, Inc.

    Inventor： Brandon M. Barber ,  Mike Basford ,  Michael R. Dowdy ,  Martin D. Gardner

    IPC: G01R31/67 ,  G01R31/71

    CPC classification number: G01R31/67 ,  G01R31/71

    Abstract: A test system for an electrical system includes a slot array having a plurality of slots and a plurality of recesses formed therethrough, a plurality of mounts in which each mount of the plurality of mounts is positioned within a respective recess of the plurality of recesses to align with a respective slot of the plurality of slots, a connector port having a plurality of pins, and a plurality of conductors in which each conductor of the plurality of conductors extends from a respective pin of the plurality of pins to a respective mount of the plurality of mounts. Each mount of the plurality of mounts is configured to receive an additional conductor via a corresponding slot of the plurality of slots to electrically couple the additional conductor to a corresponding pin of the plurality of pins via a corresponding conductor of the plurality of conductors.

    Sound attenuator for a terminal unit
    156.
    发明授权
    Sound attenuator for a terminal unit 有权

    公开(公告)号：US11898771B2

    公开(公告)日：2024-02-13

    申请号：US17344529

    申请日：2021-06-10

    Applicant: Johnson Controls Technology Company

    Inventor： Abhijeet R. Salunkke ,  Tarun Dogra ,  Sushilkumar D. Gorad ,  Parmeshwar G. Patil ,  Timothy J. Wilson ,  Vinothkumar Muthu ,  Tyler J. Williams

    IPC: F24F13/24 ,  G10K11/16

    CPC classification number: F24F13/24 ,  G10K11/161

    Abstract: A terminal unit for a heating, ventilation, and air conditioning (HVAC) system includes a housing defining a plenum and having a first panel and a second panel disposed opposite each other. The first panel has a first outlet opening and a second outlet opening, and the second panel has a first inlet opening configured to receive a first air flow and a second inlet opening configured to receive a second air flow. The terminal unit includes a sound attenuator including an inlet configured to receive the first air flow and an outlet configured to discharge the first air flow into the housing via the first inlet opening. The terminal unit further includes first and second blowers. The first blower is configured to discharge air from the plenum via the first outlet opening, and the second blower is configured to discharge air from the plenum via the second outlet opening.

    Hardware accelerators using shared interface registers
    159.
    发明授权
    Hardware accelerators using shared interface registers 有权

    公开(公告)号：US11893419B2

    公开(公告)日：2024-02-06

    申请号：US17149422

    申请日：2021-01-14

    Applicant: Apple Inc.

    Inventor： Mahesh B. Chappalli

    IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48

    CPC classification number: G06F9/5016 ,  G06F9/485 ,  G06F9/4812 ,  G06F9/4881

    Abstract: Methods and systems include processors and hardware accelerators. The processor initiates a first process in a first hardware accelerator configured to aid the processor in performing the first process. The processor initiates the first process using one or more interface registers. The processor performs additional processing while the first hardware accelerator performs the first process after initiation of the first process. The processor also initiates a second process in a second hardware accelerator configured to aid the processor in performing a second process. Moreover, the processor initiates the second process using the one or more interface registers.

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