公开(公告)号：US11719895B1

公开(公告)日：2023-08-08

申请号：US17679188

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Nicholas Polomoff ,  Keith Donegan ,  Qizhi Liu ,  Steven M. Shank

IPC: G02B6/42 ,  H01S5/02251 ,  G02B1/00

CPC classification number: G02B6/4212 ,  G02B6/421 ,  G02B6/4245 ,  H01S5/02251 ,  G02B1/002

Abstract: Structures including an edge coupler, and methods of fabricating a structure that includes an edge coupler. The structure includes an edge coupler having a waveguide core with an end surface and a longitudinal axis. The end surface defines a plane tilted in a first direction at a first acute angle relative to the longitudinal axis and tilted in a second direction at a second acute angle relative to the longitudinal axis. The second direction differs from the first direction.

公开(公告)号：US20230244033A1

公开(公告)日：2023-08-03

申请号：US17588440

申请日：2022-01-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Judson Holt

IPC: G02B6/136

CPC classification number: G02B6/136 ,  G02B2006/12061

Abstract: Waveguide structures and methods of fabricating a waveguide structure. The structure includes a first waveguide core, a second waveguide core, and a third waveguide core adjacent to the first waveguide core and the second waveguide core. The third waveguide core is laterally separated from the first waveguide core by a first slot, and the third waveguide core is laterally separated from the second waveguide core by a second slot. The first waveguide core and the second waveguide core comprise a first material, and the third waveguide core comprises a second material that is different in composition from the first material.

公开(公告)号：US20230229028A1

公开(公告)日：2023-07-20

申请号：US18125165

申请日：2023-03-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kevin K. Dezfulian

IPC: H01P5/04 ,  H01P1/18

CPC classification number: H01P5/04 ,  H01P1/182

Abstract: Structures including an electro-optical phase shifter and methods of fabricating a structure including an electro-optical phase shifter. The structure includes a waveguide core on a semiconductor substrate, and an interconnect structure over the waveguide core and the semiconductor substrate. The waveguide core includes a phase shifter, and the interconnect structure includes a slotted shield and a transmission line coupled to the phase shifter. The slotted shield includes segments that are separated by slots. The slotted shield is positioned between the transmission line and the substrate.

公开(公告)号：US20230223462A1

公开(公告)日：2023-07-13

申请号：US17657154

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/73 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/73 ,  H01L29/66234 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/0653

Abstract: Embodiments of the disclosure provide a bipolar transistor structure including a semiconductor fin on a substrate. The semiconductor fin has a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. A first emitter/collector (E/C) material is adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin. The first E/C material has a second doping type opposite the first doping type. A second E/C material is adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin. The second E/C material has the second doping type. A width of the first E/C material is different from a width of the second E/C material.

公开(公告)号：US20230223425A1

公开(公告)日：2023-07-13

申请号：US18188521

申请日：2023-03-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael J. Zierak ,  Siva P. Adusumilli ,  Yves T. Ngu ,  Steven M. Shank

IPC: H01L21/20

CPC classification number: H01L28/20

Abstract: Embodiments of the disclosure provide a method, including forming a shallow trench isolation (STI) in a substrate. The method further includes doping the substrate with a noble dopant, thereby forming a disordered crystallographic layer under the STI. The method also includes converting the disordered crystallographic layer to a doped buried polysilicon layer under the STI and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The method includes forming a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer.

公开(公告)号：US20230223254A1

公开(公告)日：2023-07-13

申请号：US17571932

申请日：2022-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Mark Levy ,  Alvin Joseph ,  Siva P. Adusumilli

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L27/085 ,  H01L21/762

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/76224 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/66462 ,  H01L21/02433

Abstract: Structures including a compound-semiconductor-based device and a silicon-based device integrated on a semiconductor substrate and methods of forming such structures. The structure includes a first semiconductor layer having a top surface and a faceted surface that fully surrounds the top surface. The top surface has a first surface normal, and the faceted surface has a second surface normal that is inclined relative to the first surface normal. A layer stack that includes second semiconductor layers is positioned on the faceted surface of the first semiconductor layer. Each of the second semiconductor layers contains a compound semiconductor material. A silicon-based device is located on the top surface of the first semiconductor layer, and a compound-semiconductor-based device is located on the layer stack.

公开(公告)号：US20230215917A1

公开(公告)日：2023-07-06

申请号：US17569897

申请日：2022-01-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali RAZAVIEH ,  Haiting WANG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/66666

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a vertical nanowire channel region and methods of manufacture. The structure includes: a bottom source/drain region; a top source/drain region; a gate structure extending between the bottom source/drain region and the top source/drain region; and a vertical nanowire in a channel region of the gate structure.

公开(公告)号：US20230207639A1

公开(公告)日：2023-06-29

申请号：US18174052

申请日：2023-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L29/401 ,  H01L29/7786 ,  H01L29/66462 ,  H01L29/41766 ,  H01L29/42316 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US11686901B2

公开(公告)日：2023-06-27

申请号：US17448804

申请日：2021-09-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Aboketaf Abdelsalam ,  Yusheng Bian

IPC: G02B6/27

CPC classification number: G02B6/2773

Abstract: Embodiments of the disclosure provide an optical polarizer with a varying vertical thickness, and methods to form the same. An optical polarizer according to the disclosure may include a first waveguide core over a semiconductor substrate. A first cladding material is on at least an upper surface of the first waveguide core. A second waveguide core over the first waveguide core and above the first cladding material. The second waveguide core includes a first segment having a vertical thickness that varies along a length of the first segment. A second cladding material is at least partially surrounding the second waveguide core. Transfer of one of a transverse electric (TE) mode signal and a transverse magnetic (TM) mode signal from the first waveguide core to the second waveguide core occurs between the first segment of the second waveguide core and the first waveguide core.

公开(公告)号：US20230197798A1

公开(公告)日：2023-06-22

申请号：US17645738

申请日：2021-12-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： JOHNATAN AVRAHAM KANTAROVSKY

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

CPC classification number: H01L29/404 ,  H01L21/765 ,  H01L21/7605 ,  H01L29/7786 ,  H01L29/42316 ,  H01L29/66462

Abstract: A transistor structure is provided, the transistor structure comprising a source, a drain, and a gate between the source and the drain. The gate may have a top surface. A first field plate may be between the source and the drain. The first field plate may be L-shaped and having a vertical portion over a horizontal portion. A top surface of the vertical portion of the first field plate may be at least as high as the top surface of the gate. A second field plate, whereby the second field plate may be connected to the gate and the second field plate may partially overlap the horizontal portion of the first field plate.