公开(公告)号：US20060273409A1

公开(公告)日：2006-12-07

申请号：US11134897

申请日：2005-05-23

Applicant: Wen-Chin Lee ,  Chung-Hu Ke ,  Min-Hwa Chi

Inventor： Wen-Chin Lee ,  Chung-Hu Ke ,  Min-Hwa Chi

IPC: H01L29/76

CPC classification number: H01L29/7839 ,  H01L21/26506 ,  H01L21/28097 ,  H01L21/32155 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66643

Abstract: A semiconductor device having a metal/metal silicide gate and a Schottky source/drain and a method of forming the same are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a metal or metal silicide gate electrode having a work function of less than about 4.3 eV or greater than about 4.9 eV overlying the gate dielectric, a spacer having a thickness of less than about 100 Å on a side of the gate electrode, and a Schottky source/drain having a work function of less than about 4.3 eV or greater than about 4.9 eV wherein the Schottky source/drain region overlaps the gate electrode. The Schottky source/drain region preferably has a thickness of less than about 300 Å.

Abstract translation: 提供了具有金属/金属硅化物栅极和肖特基源极/漏极的半导体器件及其形成方法。 半导体器件包括覆盖半导体衬底的栅极电介质，金属或金属硅化物栅电极，其功函数小于约4.3eV或大于约4.9eV，覆盖在栅极电介质上，具有小于约100的厚度的间隔物 并且肖特基源/漏极具有小于约4.3eV或大于约4.9eV的功函数，其中肖特基源极/漏极区与栅电极重叠。 肖特基源极/漏极区优选具有小于约的厚度。

公开(公告)号：US20060208336A1

公开(公告)日：2006-09-21

申请号：US11409405

申请日：2006-04-21

Applicant: Wen-Chin Lee ,  Chung-Hu Ke ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ke ,  Chenming Hu

IPC: H01L29/00

CPC classification number: H01L29/78 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76232 ,  H01L29/7846

Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

公开(公告)号：US07101742B2

公开(公告)日：2006-09-05

申请号：US10639170

申请日：2003-08-12

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/336

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

Abstract translation: 晶体管包括覆盖沟道区的栅极电介质。 源极区域和漏极区域位于沟道区域的相对侧上。 沟道区由第一半导体材料形成，源极和漏极区由第二半导体材料形成。 栅极电极覆盖栅极电介质。 在栅电极的侧壁上形成一对间隔物。 每个间隔件包括邻近通道区域的空隙。 高应力膜可以覆盖栅电极和间隔物。

公开(公告)号：US07098119B2

公开(公告)日：2006-08-29

申请号：US10845374

申请日：2004-05-13

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L29/06

CPC classification number: H01L29/1054 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method is disclosed for forming a semiconductor device using strained silicon. After forming a first substrate material with a first natural lattice constant on a device substrate and a second substrate material with a second natural lattice constant on the first substrate material, a channel, source and drain regions of a field effective transistor are further defined using the first and second substrate materials. After implanting one or more impurity materials to the source and drain regions, and the transistor goes through an annealing process using a high speed heat source other than a Tungsten-Halogen lamp.

Abstract translation: 公开了一种使用应变硅形成半导体器件的方法。 在第一衬底材料上形成具有第一自然晶格常数的第一衬底材料和在第一衬底材料上具有第二自然晶格常数的第二衬底材料之后，使用所述第一衬底材料的场效应晶体管的沟道，源极和漏极区域进一步限定 第一和第二基板材料。 在将一种或多种杂质材料注入到源极和漏极区域之后，并且晶体管经历使用除了钨 - 卤素灯之外的高速热源的退火工艺。

公开(公告)号：US20060108999A1

公开(公告)日：2006-05-25

申请号：US10991370

申请日：2004-11-19

Applicant: Wen-Chin Lee ,  Shang-Hao Chen

Inventor： Wen-Chin Lee ,  Shang-Hao Chen

IPC: G01B7/30

CPC classification number: G06F3/0362

Abstract: A precise, consistent, reliable, and high resolution magnetism metric controller applied in electronic and information devices is comprised of a scrolling wheel mechanism to drive by rotation a permanent magnet to retrieve signals of changed magnetic field due to displacement of magnetic poles of the permanent magnet.

Abstract translation: 应用于电子信息设备的精确，一致，可靠，高分辨率的磁力度量控制器包括一个滚动轮机构，通过旋转永久磁铁来驱动，以便通过永久磁铁的磁极位移来检索变化的磁场的信号 。

公开(公告)号：US07045836B2

公开(公告)日：2006-05-16

申请号：US10657616

申请日：2003-09-08

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L21/00

CPC classification number: H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76232 ,  H01L21/823412 ,  H01L29/1054 ,  H01L29/66651

Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

公开(公告)号：US20060039183A1

公开(公告)日：2006-02-23

申请号：US10850855

申请日：2004-05-21

Applicant: Wen Lin ,  Denny Tang ,  Chien-Chung Hung ,  Wen-Chin Lee

Inventor： Wen Lin ,  Denny Tang ,  Chien-Chung Hung ,  Wen-Chin Lee

IPC: G11C11/00

CPC classification number: G11C11/5607 ,  G11C11/16

Abstract: A memory cell including a switching element having a source and a drain, a first magnetic tunnel junction (MTJ) device, and a second MTJ device. The first MTJ device has a first tunneling junction resistance and is coupled to a first one of the switching element source and drain. The second MTJ device has a second tunneling junction resistance and is coupled to a second one of the switching element source and drain. The second resistance is substantially less than the first resistance.

Abstract translation: 一种存储单元，包括具有源极和漏极的开关元件，第一磁性隧道结（MTJ）器件和第二MTJ器件。 第一MTJ器件具有第一隧道结电阻并且耦合到开关元件源极和漏极中的第一个。 第二MTJ器件具有第二隧道结电阻并且耦合到开关元件源极和漏极中的第二个。 第二阻力远小于第一阻力。

公开(公告)号：US20050167777A1

公开(公告)日：2005-08-04

申请号：US10917196

申请日：2004-08-12

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: H01L21/762 ,  H01L21/00 ,  H01L21/8234 ,  H01L29/94 ,  H01L31/113

CPC classification number: H01L21/76232 ,  H01L21/76283

Abstract: A method comprises providing a substrate having an active layer, forming an isolation trench in the active layer, and forming at least one bumper substantially filling at least one divot formed at an interface between the active layer and the isolation trench during isolation trench formation.

Abstract translation: 一种方法包括提供具有有源层的衬底，在有源层中形成隔离沟槽，以及形成至少一个缓冲器，其基本上填充在隔离沟槽形成期间在有源层和隔离沟槽之间的界面处形成的至少一个纹路。

公开(公告)号：US06902965B2

公开(公告)日：2005-06-07

申请号：US10699574

申请日：2003-10-31

Applicant: Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/78 ,  H01L31/0328 ,  H01L31/072

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at lease part of the first trench, and the second trench is at least partially filled with an insulating material.

Abstract translation: 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于基底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 第二沟槽的至少一部分与第一沟槽的至少部分对准，并且第二沟槽至少部分地填充有绝缘材料。

公开(公告)号：US06900502B2

公开(公告)日：2005-05-31

申请号：US10407761

申请日：2003-04-03

Applicant: Chung-Hu Ge ,  Chao-Hsuing Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Chao-Hsuing Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/00 ,  H01L21/30 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/02 ,  H01L29/72 ,  H01L29/772

CPC classification number: H01L21/823807 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7848

Abstract: A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

Abstract translation: 半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。 第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。 第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。