公开(公告)号：US20130056815A1

公开(公告)日：2013-03-07

申请号：US13420745

申请日：2012-03-15

申请人： Megumi ISHIDUKI ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

发明人： Megumi ISHIDUKI ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/42344

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating flm provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating flm in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer.

摘要翻译： 根据一个实施例，一种非易失性半导体存储器件包括：第一层叠体; 记忆膜; 设置在记忆膜内部的第一通道体层; 设置在第一层叠体上的层间绝缘膜; 具有选择栅电极层的第二层叠体和第二绝缘层; 栅极绝缘膜，设置在与所述第一孔连通的第二孔的侧壁上，并且在所述第二层叠体的层叠方向上贯通所述第二层叠体和所述层间绝缘膜; 以及设置在第二孔中的栅极绝缘膜内部的第二沟道体层。 选择栅电极层的上端的第二孔的第一孔径比选择栅电极层的下端的第二孔的第二孔径小。

公开(公告)号：US08669608B2

公开(公告)日：2014-03-11

申请号：US13419984

申请日：2012-03-14

申请人： Mitsuru Sato ,  Megumi Ishiduki ,  Masaru Kidoh ,  Atsushi Konno ,  Yoshihiro Akutsu ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata

发明人： Mitsuru Sato ,  Megumi Ishiduki ,  Masaru Kidoh ,  Atsushi Konno ,  Yoshihiro Akutsu ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L21/265 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/66833

摘要： According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.

摘要翻译： 根据一个实施例，一种用于制造非易失性半导体存储装置的方法包括： 形成第一和第二堆叠体; 形成穿过所述第一层叠体的通孔，与所述第一部分连通并穿过选择栅极的第二部分，以及与所述第二部分连通并穿透第二绝缘层的第三部分; 形成记忆膜，栅极绝缘膜和通道体; 在通道体内形成第三绝缘层; 在第三部分内部的边界部分上方形成第一嵌入部分; 通过去除第三部分中的第一嵌入部分和第三绝缘层的一部分的一部分来暴露通道体; 以及在所述第三部分内部嵌入包含比所述第一嵌入部分上方的所述第一嵌入部分杂质浓度高的硅的第二嵌入部分。

公开(公告)号：US07276750B2

公开(公告)日：2007-10-02

申请号：US10922228

申请日：2004-08-20

申请人： Masaru Kito ,  Masaru Kido ,  Hideaki Aochi ,  Toshiharu Tanaka ,  Ryota Katsumata ,  Hideki Inokuma ,  Yoichi Takegawa

发明人： Masaru Kito ,  Masaru Kido ,  Hideaki Aochi ,  Toshiharu Tanaka ,  Ryota Katsumata ,  Hideki Inokuma ,  Yoichi Takegawa

IPC分类号： H01L27/08 ,  H01L31/00 ,  H01L29/76 ,  H01L29/06

CPC分类号： H01L27/10867 ,  H01L29/945 ,  Y10S257/906

摘要： A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.

摘要翻译： 半导体器件包括具有沟槽的半导体衬底; 电容器 环状氧化膜，布置在电容器上方的沟槽的一侧的一部分上; 存储节点，其布置在所述沟槽的上部中的所述环状氧化物膜的一侧，并且电连接到所述电容器的存储电极; 设置在所述半导体衬底的表面上并具有与所述沟槽接触的源极区域的选择晶体管; 覆盖源区一侧的间隔物; 以及布置在间隔件，源区域和存储节点上的表面带接触件。

公开(公告)号：US07135368B2

公开(公告)日：2006-11-14

申请号：US11044896

申请日：2005-01-27

申请人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi

发明人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A method of fabricating a semiconductor memory device, comprising recess-etching a major surface of a semiconductor substrate, thereby forming a pillar that becomes a device formation region; burying an insulation film in the recess-etched region, thereby forming a device isolation region; burying a first oxide film at a side wall of the pillar on the device isolation region; forming a second oxide film on an upper part of the pillar; and removing an upper part of the first oxide film using the second oxide film as a mask, thereby exposing an upper surface and an upper part of the side wall of the pillar; and the method, comprising forming a conductive material on the exposed upper surface and the exposed upper part of the side wall of the pillar, thereby forming a surface strap that electrically connects the capacitor and the second activation region.

摘要翻译： 一种制造半导体存储器件的方法，包括凹入蚀刻半导体衬底的主表面，从而形成成为器件形成区域的柱; 在凹陷蚀刻区域中埋设绝缘膜，由此形成器件隔离区域; 在器件隔离区域上的柱的侧壁上埋设第一氧化物膜; 在柱的上部形成第二氧化膜; 并使用第二氧化膜作为掩模去除第一氧化物膜的上部，从而暴露柱的侧壁的上表面和上部; 该方法包括在暴露的上表面和柱的侧壁的暴露的上部形成导电材料，从而形成电连接电容器和第二激活区域的表面带。

公开(公告)号：US20060145228A1

公开(公告)日：2006-07-06

申请号：US11311268

申请日：2005-12-20

申请人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

发明人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

IPC分类号： H01L29/94

CPC分类号： H01L29/66651 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/1037 ,  H01L29/945

摘要： A semiconductor memory device comprising a semiconductor substrate, element isolating regions formed on the semiconductor substrate, an element forming region provided between the element isolating regions on the semiconductor substrate, the element forming region having a protruding portion, a transistor having a channel formed in the protruding portion of the element forming region, and a capacitor formed in or on the semiconductor substrate to be connected to the transistor, wherein the protruding portion in the element forming region includes first and second inclined and opposed planes arranged along a channel width direction of the transistor, and an upper plane provided between the first and second inclined planes.

摘要翻译： 一种半导体存储器件，包括半导体衬底，形成在半导体衬底上的元件隔离区域，设置在半导体衬底上的元件隔离区域之间的元件形成区域，具有突出部分的元件形成区域， 所述元件形成区域的突出部分和形成在所述半导体衬底中或与所述晶体管连接的电容器，其中所述元件形成区域中的所述突出部分包括沿着所述晶体管的沟道宽度方向布置的第一和第二倾斜和相对的平面 晶体管，以及设置在第一和第二倾斜平面之间的上平面。

公开(公告)号：US20060289905A1

公开(公告)日：2006-12-28

申请号：US11442352

申请日：2006-05-30

申请人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

发明人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

IPC分类号： H01L29/76

CPC分类号： H01L29/1037 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

摘要： A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel region, each of the projected epitaxial silicon regions having a triangular ridge portion, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件，包括形成在所述半导体衬底上的至少一个FET，其中所述FET包括源极区，漏极区，形成在所述源极和漏极区之间的沟道区，并且包括沿宽度方向布置的多个投影外延硅区 的沟道区域，每个投影的外延硅区域具有三角形脊部分，形成在沟道区域上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。

公开(公告)号：US20050101094A1

公开(公告)日：2005-05-12

申请号：US10922228

申请日：2004-08-20

申请人： Masaru Kito ,  Masaru Kido ,  Hideaki Aochi ,  Toshiharu Tanaka ,  Ryota Katsumata ,  Hideki Inokuma ,  Yoichi Takegawa

发明人： Masaru Kito ,  Masaru Kido ,  Hideaki Aochi ,  Toshiharu Tanaka ,  Ryota Katsumata ,  Hideki Inokuma ,  Yoichi Takegawa

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/336 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10867 ,  H01L29/945 ,  Y10S257/906

摘要： A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.

摘要翻译： 半导体器件包括具有沟槽的半导体衬底; 电容器 环状氧化膜，布置在电容器上方的沟槽的一侧的一部分上; 存储节点，其布置在所述沟槽的上部中的所述环状氧化物膜的一侧，并且电连接到所述电容器的存储电极; 设置在所述半导体衬底的表面上并具有与所述沟槽接触的源极区域的选择晶体管; 覆盖源区一侧的间隔物; 以及布置在间隔件，源区域和存储节点上的表面带接触件。

公开(公告)号：US20050127420A1

公开(公告)日：2005-06-16

申请号：US11044896

申请日：2005-01-27

申请人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi

发明人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/786 ,  H01L31/119

CPC分类号： H01L27/10861 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A method of fabricating a semiconductor memory device, comprising recess-etching a major surface of a semiconductor substrate, thereby forming a pillar that becomes a device formation region; burying an insulation film in the recess-etched region, thereby forming a device isolation region; burying a first oxide film at a side wall of the pillar on the device isolation region; forming a second oxide film on an upper part of the pillar; and removing an upper part of the first oxide film using the second oxide film as a mask, thereby exposing an upper surface and an upper part of the side wall of the pillar; and the method, comprising forming a conductive material on the exposed upper surface and the exposed upper part of the side wall of the pillar, thereby forming a surface strap that electrically connects the capacitor and the second activation region.

摘要翻译： 一种制造半导体存储器件的方法，包括凹入蚀刻半导体衬底的主表面，从而形成成为器件形成区域的柱; 在凹陷蚀刻区域中埋设绝缘膜，由此形成器件隔离区域; 在器件隔离区域上的柱的侧壁上埋设第一氧化物膜; 在柱的上部形成第二氧化膜; 并使用第二氧化膜作为掩模去除第一氧化物膜的上部，从而暴露柱的侧壁的上表面和上部; 该方法包括在暴露的上表面和柱的侧壁的暴露的上部形成导电材料，从而形成电连接电容器和第二激活区域的表面带。

公开(公告)号：US07391068B2

公开(公告)日：2008-06-24

申请号：US11442352

申请日：2006-05-30

申请人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

发明人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

IPC分类号： H01L29/00

CPC分类号： H01L29/1037 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

摘要： A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel region, each of the projected epitaxial silicon regions having a triangular ridge portion, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件，包括形成在所述半导体衬底上的至少一个FET，其中所述FET包括源极区，漏极区，形成在所述源极和漏极区之间的沟道区，并且包括沿宽度方向布置的多个投影外延硅区 的沟道区域，每个投影的外延硅区域具有三角形脊部分，形成在沟道区域上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。

公开(公告)号：US06867450B2

公开(公告)日：2005-03-15

申请号：US10644415

申请日：2003-08-20

申请人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi

发明人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/786 ,  H01L31/119

CPC分类号： H01L27/10861 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor memory device includes memory cells each having a trench capacitor and a fin-gate-type MOSFET that selects the trench capacitor. One of activation regions of the MOSFET, which are provided in a pillar, and one of electrodes of the trench capacitor are electrically connected by a surface strap. The surface strap contacts an upper surface and an upper part of a side wall of the pillar.

摘要翻译： 半导体存储器件包括各自具有沟槽电容器和选择沟槽电容器的鳍栅型MOSFET的存储单元。 设置在柱中的MOSFET的激活区域和沟槽电容器的电极中的一个电极通过表面带电连接。 表面带接触柱的侧壁的上表面和上部。