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    System-level timing budget improvements
    151.
    发明授权
    System-level timing budget improvements 有权

    公开(公告)号：US11295793B2

    公开(公告)日：2022-04-05

    申请号：US16781949

    申请日：2020-02-04

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim

    IPC: G06F12/00 ,  G11C7/22 ,  G06F1/12 ,  G06F13/16

    Abstract: Methods, systems, and devices for system-level timing budget improvements are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.

    Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
    153.
    发明授权
    Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle 有权

    公开(公告)号：US11250893B2

    公开(公告)日：2022-02-15

    申请号：US17071107

    申请日：2020-10-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kang-Yong Kim

    IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/156 ,  G11C7/10

    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

    APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPROVING CLOCK DUTY CYCLE
    154.
    发明申请
    APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPROVING CLOCK DUTY CYCLE 有权

    公开(公告)号：US20220028438A1

    公开(公告)日：2022-01-27

    申请号：US17495082

    申请日：2021-10-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kang-Yong Kim

    IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/156 ,  G11C7/10

    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

    APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SIGNALS
    155.
    发明申请
    APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SIGNALS 审中-公开

    公开(公告)号：US20200381025A1

    公开(公告)日：2020-12-03

    申请号：US16875798

    申请日：2020-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim

    IPC: G11C7/10 ,  G11C8/18 ,  G11C8/10

    Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

    Apparatuses and methods for duty cycle error correction of clock signals
    156.
    发明授权
    Apparatuses and methods for duty cycle error correction of clock signals 有权

    公开(公告)号：US10529398B1

    公开(公告)日：2020-01-07

    申请号：US16551981

    申请日：2019-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

    IPC: G11C7/22 ,  G11C8/18 ,  G11C16/32 ,  G11C16/28 ,  G11C16/08

    Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.

    Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal
    159.
    发明授权
    Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal 有权

    公开(公告)号：US10210918B2

    公开(公告)日：2019-02-19

    申请号：US15445935

    申请日：2017-02-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

    IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076

    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

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